Clock-synchronized input circuit and semiconductor memory device

Details Clock-synchronized input circuit and semiconductor memory device Clock-synchronized input circuit and semiconductor memory device

1997-12-31

1999-06-15

Nelms, David

Static information storage and retrieval

Addressing

Sync/clocking

36518907, 365191, G11C 800, G11C 700

Patent

active

059128585

ABSTRACT:
A semiconductor memory device, to which a plurality of command signals are supplied in synchronous with a clock, comprises a plurality of input circuits, having a sampling unit for inputting said command signals and said clock and sampling said command signals in synchronous with said clock, and an output unit for outputting said sampled command signals; a command decoder for receiving the command signals output by said plurality of input circuits, decoding said plurality of command signals and generating a corresponding control signal; a memory element, which implements a variety of operational modes in response to said control signals; an output timing signal generator circuit, having a circuit architecture equivalent to at least the sampling unit of said input circuit, for sampling a predetermined signal level in synchronous with said clock, and for generating an output timing signal based on the timing of the operational delay time of said sampling unit; and wherein said input circuit outputs said sampled command signals in response to said output timing signal.

REFERENCES:
patent: 5394373 (1995-02-01), Kawamoto
patent: 5566108 (1996-10-01), Kitamura
patent: 5602798 (1997-02-01), Sato et al.

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