Clock synchronized delay scheme using edge-triggered delay lines

Details Clock synchronized delay scheme using edge-triggered delay lines Clock synchronized delay scheme using edge-triggered delay lines

1998-03-25

2000-08-29

Chin, Stephen

Pulse or digital communications

Synchronizers

327277, 327161, 327263, 327276, 327284, 713401, H04L 700, H03L 700

Patent

active

061119253

ABSTRACT:
A timing signal synchronization circuit to align an internal timing clock within an integrated circuit with an external system clock with minimum skew and within one cycle of the external system clock is disclosed. A timing signal synchronization circuit has an input buffer subcircuit to receive and delay the external system clock. A fixed delay line circuit is connected to the input buffer subcircuit to delay the received external system clock by a second delay factor to create a first timing signal. The first timing signal is the input to a first and a second measurement delay line. Each will respectively measure a first part and a second part of a period of the first timing signal. A first latch array will receive the measurement and create a first latch signal. A second latch array will receive the measurement and create a second latch signal. A variable delay line will receive the first and second latch signals, and adjust a delay time to values of the measurements of the first and second parts of the period of the first timing signal less the second delay factor. The variable delay line will receive and delay the first timing signal by the delay time to create a second timing signal. An internal buffer subcircuit will receive, buffer, amplify, and delay by a third delay factor the second timing signal to create the internal timing clock that is synchronized with the external system clock.

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"A 2.5v Delay Locked Loop For An 18mb, 500 mbls DRAM" T. Lee et al. IEEE International Solid State Circuits Conf. Paper # FA 18.6, p. 300, 1994.
"A 1 psJitter 2 clock Cycle Lock Time CMOS Digital clock Generator Based on An Interlequed Synchronous Mirror Delay Scheme", T. Saeski et al, Digest of Technical Papers--Symposium on vLSI Circuit, IEEE, 1997.
T. Saeki et al. "A 2.5ns clock access 250mhz 256mb 5DRAM with a synchronous Mirror Delay", IEEE 3International solid State Circuits, Conference Paper# SP23.4, p. 374-S, 1996.

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