Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
2006-11-14
2006-11-14
Vu, Huy D. (Department: 2616)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S503000, C375S354000
Reexamination Certificate
active
07136388
ABSTRACT:
A clock synchronization scheme for use with an access network element having scalable architecture. A point-to-point, high-speed communication link provided between two adjacent banks of the access network element logically interconnects a plurality of banks in a linear stack, thereby creating a stackplane hierarchy for local traffic. A primary bank includes a central master timing and frame alignment control block operable based on a master reference clock. A secondary bank immediately coupled to the primary bank is operable to synchronize its local clock based on a delay preset signal provided by the primary bank. Each remaining secondary bank is operable to synchronize its local clock based on the delay preset signal provided by a local master timing control block disposed in the secondary bank immediately above it.
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Blackburn Bracy James
Friedrichs Eric
Alcatel
Danamraj & Youst P.C.
Sewell V. Lawrence
Shand Roberta A.
Slaton Bobby D.
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