Patent
1981-09-25
1984-10-02
Heyman, John S.
328 63, 328 72, 328 55, 328155, H03K 301, H03K 117
Patent
active
044750854
ABSTRACT:
A clock synchronization signal generating circuit includes a clock synchronizing circuit having a scale variable counter for counting a source clock signal from a source clock generator and a control circuit for controlling the scale of counter responsive to the phase difference between an input clock signal supplied from a digital operation system and an output signal from the scale variable counter, and a clock circuit including a counter for counting in n-scale mode a source clock signal from the source clock generator. The scale variable counter is selectively set to (n-1)-, n- or (n+1)-scale mode responsive to the control signal from the control circuit to generate an output signal which is clock-synchronized with the input clock signal.
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Electrical Design News, vol. 17, No. 6, Mar. 15, 1972, pp. 36-39, Denver (USA); D. A. Johnson.
Honda Shunsuke
Suzuki Hideo
Yahata Haruki
Callahan Timothy P.
Heyman John S.
Tokyo Shibaura Denki Kabushiki Kaisha
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