Clock synchronization semiconductor memory device

Details Clock synchronization semiconductor memory device Clock synchronization semiconductor memory device

2000-05-10

2002-03-05

Mai, Son (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000, C365S238500, C365S203000

Reexamination Certificate

active

06353573

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a semiconductor memory device and, more particularly, to a clock synchronization semiconductor memory device.
BACKGROUND OF THE INVENTION
In keeping up with the increasing operating frequency of a CPU, there is raised a demand for increasing the operating speed of a semiconductor memory device, such as a dynamic random access memory (DRAM). In order to meet this demand, a synchronization semiconductor memory device operating in synchronism with the external clocks exceeding 100 MHz, with a clock Period being tCK<10 ns, has made its debut. In the clock synchronization semiconductor memory device, the input/output and the operating timing of a-variety of control circuits are control led by clocks supplied from outside to enable operational control by commands (signal combination) and burst read/burst write with continuous accessing.
In the semiconductor memory device, when data is written from a writing circuit through a digit line in a memory cell selected on the memory cell array, a pre-set delay time is provided after the writing. After this delay time, pre-charging (with equalizing) from a pre-charging circuit to a digit line is executed to set the digit line at a pre-set potential. The pre-charging is executed after the pre-set delay as from the writing in order to prevent inputting of incorrect data which tends to occur if the pre-charging is executed before writing data in the memory cell. For the write recovery period of time, reference is made to, for example, the disclosure of the JP Patent Kokai JP-10-64269, the entire relevant disclosure thereof being incorporated herein by reference thereto.
In the case of the clock synchronization semiconductor memory device, the cycle from a clock (timing) at the last data writing until a clock (timing) of inputting a pre-charge command represents a write recovery period tWR, e.g., upon burst writing (likewise upon single writing). A digit line is pre-charged by inputting a pre-charge (PRE) command using a combination of control signals from an external terminal, whilst a word line is reset by resetting a row address line.
Thereupon, the reset timing of the internal row address strobe signal (RASB), that is the transition timing from the Low level to the High level, is delayed by a delay circuit, so that the word line connected to the memory cell will be reset after inputting the pre-charging command and subsequent data writing in a selected memory cell, whereby adjusting is performed on the timing of resetting of the word line selectively driven by an X-decoder (transition from the High level to the Low level).
Referring first to
FIG. 13
, schematics of an illustrative structure of an example of a conventional synchronous DRAM, as a clock synchronization semiconductor memory device, are explained. Meanwhile, in
FIG. 13
, those elements not directly related with the subject matter of the present invention, for example, a bank structure of a DRAM core, column address counter for burst control, burst length, burst type, CAS latency, mode register for storing an operational code or a refresh control circuit etc. are not shown for simplicity.
Referring to
FIG. 13
, the conventional synchronization DRAM includes a command decoder
11
, which is fed with control signals from a row address strobe ({overscore ( )}RAS) terminal, a column address strobe ({overscore ( )}CAS) terminal, a write enable ({overscore ( )}WE) terminal and a chip select ({overscore ( )}CS) terminal, as output terminals, and which decodes commands from combinations of values of these control signals; an internal clock generating circuit
10
that generates an internal clock signal I CLK from an external clock signal input to a clock input (CLK) terminal; a mask signal generating circuit
12
that generates an internal DQM signal (signal controlling the masking of an input signal and output enable) based on a DQM signal fed from an input mask/ output enable (DQM) terminal; an internal address signal generating circuit
13
that inputs and buffers an address signal, selects a bank and outputs an internal address signal; an input/output circuit
14
that receives data from a data input/output (DQ) circuit and outputs data to the DQ terminal; an internal row address strobe signal generating circuit (internal RASB signal generating circuit)
15
that outputs an internal row address strobe (RASB) signal; a word line timing adjustment circuit
16
; a CAS (column address strobe) control circuit
17
, fed with an internal clock signal ICLK, a READ signal from the command decoder
11
and a write burst signal WBST; a RAS (row address strobe) control circuit
18
, fed with the internal clock signal I CLK and an internal RASB signal; an X-decoder (XDEC)
19
fed with a row address from the internal address signal generating circuit
13
to decode the row address to select a word line; and a Y-decoder (YDEC)
20
fed with a column address from the internal address signal generating circuit
13
to decode the column address to select a digit line of a memory cell array.
An ACT (bank active) signal output from the command decoder
11
and a PRE (pre-charging) signal, output by the command decoder
11
. are input to the internal RASB signal generating circuit
15
where an internal RASB signal is generated. Meanwhile, bank selection by a pre-set bit or bits of an address signal is made upon a bank active (ACT) command. After this ACT command, commands of read (READ), write (WRITE) and pre-charging (PRE) are executed.
This internal RASB signal generating circuit
15
is constituted by e.g., a set-reset (SR) latch circuit, such that, if an ACT signal is asserted, the internal RASB signal is rendered active (low-level), whereas, if the pre-charging (PRE) signal is asserted, the internal RASB signal, which has so far been active, is reset to an inactive (high-level) state.
This internal RASB signal is input to the word line timing adjustment circuit
16
, which then generates an RAS
3
B (third row address strobe) signal controlling the word line strobe timing to supply the generated RAS
3
B signal to the X-decoder
19
. The X-decoder decodes a row address signal to select a word line. If the RAS
3
B signal is turned active, the X-decoder
19
activates the selected word line, whereas, if the RAS
3
B signal is active, the X-decoder
19
resets the row address to reset the word line.
FIG. 14
schematically shows an illustrative structure of a memory cell array
21
. A memory cell array transistor
22
, connected to digit line pairs (D/DB
—
1, D/DB
—
2, . . . ) has its gate connected to a word line from the X-decoder
19
. The digit line pairs are connected to a readout/write circuit (sense amplifier)
23
through a column switch on/off controlled by a column selection line from the Y-decoder
20
. The readout/write circuit
23
is connected through an I/O line (read/write data bus) to the input/output circuit
14
. In
FIG. 14
,
24
is a pre-charging equalizer circuit of the digit line pair receiving signals from the RAS (row address strobe) control circuit
18
of
FIG. 13
to pre-charge and equalize the digit line Pairs. Here, the pre-charge potential of the digit line pairs (D/DB
—
1, D/DB
—
2, . . . ) is at an intermediate level of the power source potentials (amplitude of the digit line).
The word line timing adjustment circuit, configured as shown in
FIG. 15
, outputs the input internal RASB signal, which has turned low from the high level, at the same time, that is without delay, while outputting the internal RASB signal, which has turned high from the low level by the assertion of the PRE-signal, as a signal RAS
3
B delayed by delay time td provided by the delay circuit
301
.
The X-decoder
19
is responsive to the resetting from the low level to the high level of this RASB
3
signal to reset the row address. As a result, the selected word line is also reset from the high level to the low level to render the memory cells nonselected.
FIG. 16
, illustrating schematics of the operation of the clock synchronization type semi

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