Clock synchronization over data transmission networks

Pulse or digital communications – Synchronizers – Frequency or phase control using synchronizing signal

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C370S514000, C348S518000

Reexamination Certificate

active

06175604

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field
The following invention disclosure is generally concerned with the synchronization of receiver and transmitter time-bases in data transmission networks and specifically concerned with a least squares linear regression technique having a fast startup phase and improved jitter absorption.
2. Prior Art
Recent developments and advances in information technologies have led to new and unanticipated problems. In particular, transfer of data from a server to a requesting client presents certain complication. In addition, the types and formats of data to be transferred have attributes which may further complicate matters. For example, video data comprises a series of still frames which must be played one after another in a predefined and well regulated time sequence. Accordingly, information relating to the image data must be transferred along with information relating to the timing of playback events. Proper transmission of video images requires a scheme to preserve signal timing attributes from a transmitting station to a receiving station.
For proper play-back, an audio-video signal is preferably played out at the same rate which it is transmitted. This is especially important in interactive systems where “real-time” properties are maintained. If a receiver clock is independent from a transmitter clock then the receiver may play frames slightly faster than it receives them and lead the system into a data starvation condition. Alternatively, if the receiver plays frames too slowly, then a data overflow condition may occur at a data buffer having a limited size.
In certain transmission networks a data stream is divided into many portions or “packets” and transmitted along various paths of the network. These packets may be subject to time delays which are random in length. Sometimes and herein referred to as “jitter”, random time delays are necessarily inherent in networks which transmit data in data subsets. Each data packet may arrive at a receiver with a total transmission time which may vary from packet to packet. Depending upon the network path and network congestion conditions, transmission time delays may be highly different between packets. For audio-video data to be useful, it must be transmitted through the packet network and played back in a manner where the time delays or network jitter does not show up as artifacts in the presentation level play back. In order to achieve this, it is necessary that a time base of the transmitting station be replicated at the receiver and thus the “clocks” of the terminal end are said to be synchronized.
Most popular processing devices of digital audio-video data, like TV decoders or PC video boards, define a syntax for coding, decoding, transport and storage of audio-video data streams. This scheme includes provision for a shared time-base between the terminal ends, i.e., the sender and the receiver. For proper processing of digital audio-video signals, it is necessary that a clock of the receiver be synchronized to a clock of the transmitter. Presently, digital audio-video signals are processed within systems which employ a phase-lock loop technique to synchronize a receiver clock to the transmitter clock. The technique is old and reliable and has made its way into many thousands of similar applications where a slave clock is necessarily coupled to a master clock. However, the technique suffers from problems which arise do to the nature of the feedback loop. A phase-locked loop may require many feedback cycles before the slave clock becomes locked to the master clock. This is especially true when the allowable error (clock cycle or frequency) is small. If the phase of the slave clock must be precisely matched with the master, then the lock may take a considerable amount of time to achieve. The period of time for the clocks to become in sync may be referred to as a “startup phase”. Accordingly, a phase-locked loop having high precision requirements may have a long startup phase. Transmission systems which employ phase-locked loop techniques are slow to realize the lock and perfect the transmission of audio-video data. While the startup phase is incomplete, an application may play audio-video data where timing artifacts show up at the presentation level.
In systems where the time to acquire a lock is short compared to the time in which a lock is held, the problem is not of serious consequence, however, for some systems the time extent of the signal is relatively short and the required lock time becomes problematic. For example, in real-time applications such as interactive teleconferencing. The first few seconds of each data exchange may suffer from a clock which is out of sync. Since the duration of any single transmission may only be of the order of a few seconds, startup phase errors due to phase-locked loop techniques become perceivable to the end user. Accordingly, it becomes desirable to find a scheme which locks a slave clock to a master clock where the time to obtain a lock is shorter than that which is associated with a phase-locked loop.
Yasuda teaches a modified phase-locked loop technique in U.S. Pat. No. 5,386,437 published Jan 31, 1995.
A primary objective of that teaching is a variable output which varies in relation to phase error to produce a desired characteristic during pull-in and during synchronization. The techniques provide for avoiding a step-like sudden change of clock frequencies. While being a significant improvement, the system remains a version of a phase-locked loop technique which has a long pull-in or start up period and is consequently not appropriate for applications requiring synchronization where the session length is short.
Inventors Witsaman et al disclose an apparatus for synchronizing a plurality of clocks in a simulcast network to a reference clock. U.S. Pat. No. 5,416,808 dated May 16, 1995 sets forth a scheme whereby a centralized reference clock keeps a time which is accessible over a large geographic area. Individual distributed clocks are manipulated in accordance with comparisons of their time with the time on the reference clock.
While the systems and inventions of the prior art are designed to achieve particular goals and objectives, some of those being no less than remarkable, these inventions have limitations which prevent their use in new ways now possible. These prior art inventions are not used and cannot be used to realize the advantages and objectives of the present invention.
SUMMARY OF THE INVENTION
Comes now, Raffaele Noro and Jean-Pierre Hubaux with an invention of apparatus and methods relating to clock synchronization over data transmission networks including a least squares linear regression technique and device for executing same, having fast startup phase and high jitter absorption. It is a primary function of these apparatus and methods to provide means of reducing the time required to reach a synchronized state while maintaining synchronization accuracy. It is a contrast to prior art methods and devices that those systems do not reach a synchronization lock without first enduring a long startup period. A fundamental difference between a phase-locked loop of the prior art and the instant invention can be found when considering handling of timing indicators which are coded onto a signal being transmitted.
In systems of the invention, an apparatus receives a data stream containing timing indicators, which are used in a least squares linear regression technique to synchronize the time-base of a transmitting station with that of a receiving station. Timing indicators, commonly called program clock references or PCRs, contain timing information and are generated at the transmitter end in accordance with a data transmission coding syntax. After data streams are received at an apparatus of the invention on a receiving end, the PCRs are separated from the base signal and are used to drive a modified least squares linear regression technique which produces timing information to reconstruct the time base of the transmitting station.
A conventional l

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Clock synchronization over data transmission networks does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Clock synchronization over data transmission networks, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock synchronization over data transmission networks will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2523764

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.