Coded data generation or conversion – Digital code to digital code converters – Data rate conversion
Reexamination Certificate
2003-01-22
2004-08-10
Jeanglaude, Jean Bruner (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
Data rate conversion
C341S050000
Reexamination Certificate
active
06774823
ABSTRACT:
TECHNICAL FIELD
The present invention relates to circuits utilizing clock signals. More specifically, the invention relates to synchronization of sampling operations in systems having more than one clock signal.
BACKGROUND
Many electronic circuits, including most complex digital systems, utilize signals called clocks. A clock is generally a signal which oscillates between two values at a regular rate, and which can be employed to control the timing of various events in a circuit. Events may be triggered by transitions in clock signals.
Examples of events and operations which typically rely on clock signals for successful execution include loading or writing data from data registers onto data lines, and sampling or reading data from data lines into registers. Loading or sampling several data bits, representing a data word, may be done by using a separate data line for each bit. Thus a plurality of data lines, referred to as a data bus, is used to carry the word from the writing to the sampling registers.
Frequently, one operation must wait until the completion of another operation or must wait until a certain state is achieved before execution. This may be the case if a multi-bit data bus is used to load or sample a word consisting of a plurality of data bits into a register that will simultaneously hold the bits of the word after it is sampled. In order for the bits of the word to be read correctly, and to avoid sampling bits accidentally remaining from previous words, synchronizing of write and read operations is required to ensure that all bits are sampled into the sampling register at the correct time.
One aspect complicating the design and operation of data transfer circuits occurs when two interacting circuits use two separate clock signals or two clock signals which are derived from a common clock signal source sometimes referred to as a “master clock.” Even if the two clock signals operate at the same frequency, it is possible for phase shifts and phase errors to occur between the two clock signals. This can cause problems to develop in systems that rely on communication or data exchange between two circuits, each having its own clock. The same is true for two parts of one circuit, each part having its own clock. If the two circuits or the two parts of the same circuit utilizing the two clock signals are coupled to one another, timing difficulties and synchronization difficulties can arise.
As an example, if a first circuit writes data onto a bus according to a first clock signal, and a second circuit samples the data from the bus according to a second clock signal, the sampling circuit must sample the bus only when the bits on the bus are in a stable state. That is, the second circuit should avoid sampling the data on the bus during transition periods during which the data signals are changing and which can lead to errors.
Similarly, errors can arise if two parts of a single circuit are exchanging data on a data bus. The discussion herein generally treats the case of two separate circuits as similar to the case of one circuit having two or more constituent parts, or sub-circuits. Also, the discussion is applicable to more than two circuits or more than two sub-circuits.
In some systems, two circuits are interfaced or coupled, with each being clocked individually or deriving a clock signal from a common master clock signal. The master clock signal operates at some frequency, which determines the frequencies of the two derived clocks for the two circuits. However, due to one or more factors, the two clocks for the individual circuits may experience a phase shift with respect to one another. For example, temperature or supply voltage variations in one or both circuits may cause variations in propagation delays through the components of one or both circuits. For example, the data to clock delay of the registers loading data to the bus and the setup and hold times of the registers reading data from the bus depend on the operating voltage and temperature.
The problems described above become even more acute in high-speed circuits. It is known that a signal line requires a finite time to achieve a transition. For example, the time required to transition between one state and another state in a binary system is finite and measurable. Currently, such transitions can be on the order of several 100 picoseconds. The cycle time in some circuits is approximately 1000 picoseconds. Such circuits, operating in the 1+ GHz frequency range, are in common use today, and new circuits will be even faster in the future.
In order for current and future systems, such as systems loading and sampling data onto and off of data bus lines, to operate without undue error, it is sometimes useful to be able to determine the relative phase shifts between two clocks in two different coupled circuits or in two parts of the same circuit and adjust the clocks of the two circuits.
SUMMARY
Various embodiments of the present invention are described in more detail below.
Accordingly, one embodiment is directed to a method for transferring data between a first circuit, having a first clock signal, and a second circuit, having a second clock signal, comprising generating a first time-shifted signal corresponding to the first clock signal; generating a second time-shifted signal corresponding to the first clock signal; comparing the first and second time-shifted signals to yield an error signal; and sampling the data during a temporal window defined by the error signal.
Another embodiment is directed to a method for timing a circuit event, comprising time-shifting a first reference signal, by a setup time, to yield a first time-shifted signal; time-shifting any of the first reference signal or a second reference signal, by a hold time, to yield a second time-shifted signal; determining an error window defined by a temporal offset between the first and the second time-shifted signals; and performing the circuit event at a time not falling within the error window.
Yet another embodiment is directed to a system for transferring data, comprising a data line, receiving data from a first circuit, said first circuit having a first clock signal; a signal generator receiving the first clock signal and producing a pseudo-signal; a first time shifter receiving the pseudo-signal and generating a first time-shifted signal; a second time shifter receiving the pseudo-signal; and generating a second time-shifted signal; and a comparator, for comparing the first and second time-shifted signals, receiving the first and second time-shifted signals and producing an error signal for synchronizing data sampling from the data line during a temporal window defined by the error signal.
REFERENCES:
patent: 5087992 (1992-02-01), Dahandeh et al.
patent: 5115208 (1992-05-01), Masdea et al.
patent: 6169970 (2001-01-01), Kleijn
Analog Devices Inc.
Jeanglaude Jean Bruner
Wolf Greenfield & Sacks P.C.
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