Clock synchronization device

Details Clock synchronization device Clock synchronization device

2006-07-11

2006-07-11

Ha, Dac V. (Department: 2634)

Pulse or digital communications

Synchronizers

C327S158000, C327S159000, C327S161000, C370S517000

Reexamination Certificate

active

07076013

ABSTRACT:
A clock synchronization device is disclosed which optimizes clock skew without increasing the number of unit delay cells by using an auxiliary delay circuit when a clock signal of ultra low frequency is inputted and improves operation frequency by using different programmable dividers to operate at different division rates when clock signals of high frequency and low frequency are inputted. Additionally, the optimum clock synchronization device may be embodied by using a replica delay unit corresponding with the package type.

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patent: 6483359 (2002-11-01), Lee
patent: 6552587 (2003-04-01), Kim et al.
patent: 6587534 (2003-07-01), Hassoun et al.
patent: 1998-0087852 (1999-12-01), None
patent: 1020000023294 (2000-04-01), None
patent: 1020010007099 (2001-01-01), None
Notice of Rejection (with translation), corresponding to Korean Patent Application Serial No. 2001-0086676, Korean Intellectual Property Office, dated Mar. 24, 2005, 6 pages (including translation).

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