Clock synchronization device

Details Clock synchronization device Clock synchronization device

2002-05-06

2003-06-24

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S141000, C341S054000, C341S063000

Reexamination Certificate

active

06583654

ABSTRACT:

BACKGROUND
1. Field of the Invention
The present invention relates to a clock synchronization device and, in particular, to a clock synchronization device including a converting unit for converting a binary-weighted code to a thermometer code, thereby decreasing a number of registers and reducing a leakage current.
2. Description of the Background Art
In general, an analog clock synchronization device (delay locked loop (DLL) or phase locked loop (PLL)) has a smaller area, a wider operation region, higher accuracy and smaller jitter property than a digital clock synchronization device. However, the analog clock synchronization device consumes considerable DC current.
Accordingly, there has been suggested a method of combining the analog and digital devices by using a digital to analog converter (DAC or D/A converter). This method controls the clock synchronization device (DLL/PLL) by generating a digital code value corresponding to a phase difference between an external clock signal and an internal code value and then generating an analog value (voltage or current) according to the generated digital code value by using the DAC.
FIG. 1
is a block diagram illustrating a conventional clock synchronization device using a thermometer code DAC. The illustrated conventional clock synchronization device includes a phase detecting unit
1
for detecting a phase difference between an internal clock signal ICLK and an external clock signal ECLK. A register unit
2
, outputs a thermometer code TC according to detection signals SFTR and SFTL received from the phase detecting unit
1
. Also included is a D/A converting unit
3
for generating an output voltage VOUT corresponding to the thermometer code TC. Finally, a clock synchronization control unit
4
generates the internal clock signal ICLK from the external clock signal ECLK according to the output voltage VOUT from the D/A converting unit
3
. The clock synchronization control unit
4
comprises a voltage controlled delay line when it is used in the DLL, but comprises a voltage controlled oscillator when it is used in the PLL.
If the number of bits of the D/A converting unit
3
is increased, the number of shift registers of the register unit
2
is increased by a multiplier of 2, thereby resulting in a large chip area and high leakage current. For example, when the D/A converting unit
3
includes 6 bits, the register unit
2
requires 64 shift registers.
To solve the foregoing problems, a binary-weighted DAC may be employed instead of the thermometer code DAC. However, linearity and monotony may be deteriorated due to a glitch in such systems.
SUMMARY OF THE INVENTION
The present disclosure provides a clock synchronization device including a converting unit for converting a binary-weighted code to a thermometer code, thereby decreasing a number of registers and finally reducing a leakage current.
According to the present disclosure, a clock synchronization device is provided that includes a phase detecting unit configured to detect a phase difference between an external clock signal and an internal clock signal. The device also includes a binary code generating unit configured to output a binary code value according to output signals received from the phase detecting unit. A code converting unit converts the binary code value received from the binary code generating unit into a thermometer code value. A digital-to-analog converting unit is included and configured to output an output voltage corresponding to the thermometer code value. Finally, a clock synchronization control unit is provided and configured to output the internal clock signal based on the external clock signal and the output voltage from the digital-to-analog converting unit.


REFERENCES:
patent: 4694259 (1987-09-01), Carickhoff et al.
patent: 5796358 (1998-08-01), Shih et al.
Notice of Rejection(with translation), corresponding to Korean Patent Application Serial No. 10-2001-0039037, Korean Intellectual Property Office, dated Jan. 23, 2003, 4 pages.

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