Clock synchronization device

Details Clock synchronization device Clock synchronization device

2002-06-27

2003-07-22

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Phase or time of phase change

C375S356000

Reexamination Certificate

active

06597298

ABSTRACT:

BACKGROUND
1. Field of the Invention
The inventions described and or claimed relate generally to clock synchronization. More particularly, they relate to a clock synchronization arrangement (apparatus and methods) capable of improving (lowering) jitter in a variable delay line VDL operating in a low frequency band with a very large gain. Operations of main and sub digital-to-analog converters are determined by a result of comparing a reference voltage with an output voltage of the digital-to-analog converter.
2. Description of Related Art
Generally, a clock synchronization device of the analog type (delayed locked loop DLL or phase locked loop PLL) occupies a smaller area, and has a larger operating region, a higher precision and a smaller jitter than a digital type, but it consumes a large DC current.
Therefore, a hybrid type clock synchronization device including both analog and digital components is being used. An example of such a clock synchronization device is one that uses a digital-to-analog converter DAC. A digital code corresponding to a phase difference between an external clock signal and an internal clock signal is generated. An analog value (voltage or current) is generated from the digital code, which, in turn, controls the clock synchronization device.
FIG. 1
(Prior Art) is a block diagram of a clock synchronization device using a known digital-to-analog converter. The clock synchronization device is constructed as a delayed locked loop DLL. The clock synchronization device includes a phase detecting unit
1
, a binary code generating unit
2
, a digital-to-analog converting unit
3
and a variable delay line VDL. The phase detecting unit
1
detects a phase difference between an external clock signal ECLK and an internal clock signal ICLK. The binary code generating unit
2
outputs a binary code BC of N bits according to a detection signal SFTR, SFTL from phase detecting unit
1
. The digital-to-analog converting unit
3
generates a voltage VDAC corresponding to the binary code BC of the binary code generating unit
2
. The variable delay line VDL
4
delays the external clock signal ECLK for a predetermined time and outputs an internal clock signal ICLK by using the output voltage VDAC from the digital-to-analog converting unit
3
.
FIG. 2
is a circuit diagram illustrating a detail circuit of a delay cell of a variable delay line shown in the block diagram of
FIG. 1
(Prior Art). The variable delay line
4
includes chains of a plurality of delay cells.
Each delay cell includes a variable current source
5
for generating current according to the output voltage VDAC from the digital-to-analog converting unit
3
, an input unit
6
for receiving input signals IN and /IN (the input signals IN and /IN of the first delay cell are output voltages VDAC and NVDAC, and the input signals IN and /IN of the second through last delay cells are the output signals OUT and /OUT of the preceding delay cell), and a load
7
for determining a delay rate.
The variable current source
5
is formed of an NMOS transistor NM
0
in which an output voltage VDAC is applied to a control terminal and a source is connected to a ground voltage VSS.
The input unit
6
is formed of NMOS transistors NM
1
and NM
2
for receiving input signals IN and /IN to the control terminal. Here, the common source of the NMOS transistors NM
1
and NM
2
are connected to the drain of the NMOS transistor NM
0
. The drains of the NMOS transistors NM
1
and NM
2
form an output terminal to produce output signals OUT and /OUT, respectively.
In the variable delay line
4
comprising chains of delay cells, the output signals OUT and /OUT of an (i−1)th delay cell are inputted respectively into input signals IN and /IN of an i-th delay cell, and the output signals OUT and /OUT of the i-th delay cell are inputted respectively into input signals IN and /IN of an (i+1)th delay cell.
The delay rate TDCEL of a delay cell with respect to current I flowing in the NMOS transistor NM
0
forming the variable current source
5
of the delay cell is obtained by the following equation 1.
TDCEL
=
C
×
VPP
I
equation
⁢
 
⁢
1
Here, C represents the capacitance between the output terminals of a delay cell, and VPP represents the voltage swing width between the output terminals.
Therefore, the relation between the output voltage VDAC of the digital-to-analog converting unit
3
and the delay rate T of the variable delay line
4
has a non-linear property as shown in the graph of FIG.
3
.
If it is assumed that the unit step voltage VDEL of the digital-to-analog converting unit
3
has a linear delay property with respect to the output voltage VDAC of the digital-to-analog converting unit
3
, the unit phase resolution PRES of the clock synchronization device (here, “DLL”) can be obtained by the following equation 2.
PRES=KVDL×VDEL  equation 2
Here, KVDL represents a gain of the delay cell of the variable delay line
4
, which can be obtained by the following equation 3.
KVDL
=
ⅆ
t
ⅆ
v
equation
⁢
 
⁢
3
Here, dt represents the rate of change in unit time, and dv represents the rate of change in unit voltage. The gain KVDL of the delay cell DCEL of the variable delay line
4
is constant. Accordingly, the phase resolution is constant regardless of an input clock frequency.
Contrary to the above assumption, since the delay property of the variable delay line
4
is non-linear, the phase resolution changes as a function of clock frequency.
FIG. 3
is a graph illustrating a delay time of a variable delay line with respect to an output voltage of a digital-to-analog converting unit according to the block diagram of FIG.
1
. As illustrated in
FIG. 3
, when the output voltage VDAC of the digital-to-analog converting unit
3
reaches a predetermined voltage VREF because of a decrease in frequency, the phase resolution is sharply increased, thereby degrading the jitter of the clock synchronization device (here, “DLL”).
SUMMARY
The various inventions described and/or claimed herein provide a clock synchronization arrangement capable of improving jitter even for a low frequency clock signal by adjusting the number of input bits of a digital-to-analog converting unit according to a level of the output voltage.
There is provided a clock synchronization arrangement including a phase detector, a code generator, a digital-to-analog (D/A) converter, a level detector and a clock synchronization controller. The phase detector detects a phase difference between an external clock signal and an internal clock signal. The code generator generates codes of N bits according to the phase difference. The D/A converter generates a voltage corresponding to the codes of N bits from the code generator. The level detector compares the voltage from the D/A converter with a predetermined reference voltage, and outputs a control signal to adjust a level of the voltage from the D/A converter according to the comparing result. The clock synchronization controller outputs an internal clock signal after delaying the external clock signal for a predetermined time, wherein the predetermined time is determined by the voltage from the D/A converter.


REFERENCES:
patent: 5790608 (1998-08-01), Benayoun et al.

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