Clock synchronization control check system

Details Clock synchronization control check system Clock synchronization control check system

1994-06-13

1996-04-23

Chin, Stephen

Pulse or digital communications

Testing

Phase error or phase jitter

375371, 324 7677, H04B 346, H04B 1700

Patent

active

055110916

ABSTRACT:
A clock synchronization control check system for a digital baseband signal receiver which digitally provides a phase error to digital data generated by a digital modulator without the need for conversion of the digital data to analog data so that clock synchronization control in its demodulating section can be checked easily and precisely. In the system, a digital filter is used to suppress inter-symbol interference, and a set of filter coefficients for the digital filter is shifted along the time axis of an impulse response so as to provide a plurality of filter coefficient sets. By selecting one of the coefficient sets, a desired phase shift is given to the digital data signal.

REFERENCES:
patent: 4129831 (1978-12-01), Fink et al.
patent: 4367550 (1983-01-01), Douverne
patent: 4633465 (1986-12-01), Fitch et al.
patent: 4757519 (1988-07-01), Collison et al.
patent: 4953181 (1990-08-01), Keiper, Jr.
patent: 5333147 (1994-07-01), Nohara et al.
Liu, C.-L., and Feher, K., "A New Filtering Strategy to Combat Delay Spread", in Proceedings of the 1991 IEEE Vehicular Technology Conference, Jul. 1991, pp. 776-781.

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