Clock synchronization circuit having bidirectional delay...

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Reexamination Certificate

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Details

C327S161000, C327S294000, C327S298000

Reexamination Certificate

active

06867626

ABSTRACT:
A clock synchronization circuit includes a first delay circuit for delaying a clock signal and outputting the delayed clock signal, first and second bidirectional delay circuit strings, a first pre-stage delay circuit and a first post-stage delay circuit of variable delay time type, arranged in a pre-stage and a post-stage of the first bidirectional delay circuit string (BDDA), a second pre-stage delay circuit and a second post-stage delay circuit of variable delay time type, arranged in a pre-stage and a post-stage of the second bidirectional delay circuit string (BDDB), and a multiplexer, supplied with and multiplexing outputs of the first and second post-stage delay circuits to output the resulting signals. An output signal of the first delay circuit is supplied in common to the first and second pre-stage delay circuits. A first path composed of the first pre-stage delay circuit, first bidirectional delay circuit string and the first post-stage delay circuit and a second path composed of the second pre-stage delay circuit, second bidirectional delay circuit string and the second post-stage delay circuit are alternately switched in an interval of one cycle of the clock signal.

REFERENCES:
patent: 5870445 (1999-02-01), Farwell
patent: 6069508 (2000-05-01), Takai
patent: 6239641 (2001-05-01), Lee
patent: 6359480 (2002-03-01), Isobe et al.
patent: 6434062 (2002-08-01), Lee
patent: 6437619 (2002-08-01), Okuda et al.
patent: 6574163 (2003-06-01), Maeda
patent: 6621316 (2003-09-01), Kirsch
patent: 6703879 (2004-03-01), Okuda et al.
patent: 6727740 (2004-04-01), Kirsch
patent: 11-66854 (1999-03-01), None
patent: 02004064143 (2004-02-01), None

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