Clock synchronization circuit and operation method thereof

Details Clock synchronization circuit and operation method thereof Clock synchronization circuit and operation method thereof

2008-06-30

2010-12-21

Luu, Pho M (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S189040, C365S194000, C365S189120

Reexamination Certificate

active

07855933

ABSTRACT:
A semiconductor memory device with a clock synchronization circuit capable of performing a desired phase/frequency locking operation, without the jitter peaking phenomenon and the pattern jitter of an oscillation control voltage signal using injection locking. The device includes a phase-locked loop that detects a phase/frequency difference between a feedback clock signal and a reference clock signal to generate an oscillation control voltage signal corresponding to the detected phase/frequency difference, and generates the feedback clock signal corresponding to the oscillation control voltage signal. An injection locking oscillation unit sets up a free running frequency in response to the oscillation control voltage signal and generates an internal clock signal which is synchronized with the reference clock signal.

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Notice of Preliminary Rejection issued from Korean Intellectual Property Office on Apr. 8, 2009 with an English Translation.
Notice of Allowance issued from Korean Intellectual Property Office on Jun. 15, 2009 with an English Translation.
Notice of Allowance issued from Korean Intellectual Property Office on Nov. 3, 2009.

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