Clock synchronization

Details Clock synchronization Clock synchronization

1996-12-31

2001-01-09

Vu, Huy D. (Department: 2733)

Multiplex communications

Data flow congestion prevention or control

Control of data admission to the network

C370S395430

Reexamination Certificate

active

06172964

ABSTRACT:

FIELD OF THE INVENTION
An important issue in the design of an asynchronous communication network such as an Asynchronous Transfer Mode (ATM) network is synchronisation of the network. If the network is to be able to handle any traffic type that is inherently synchronous then it is necessary to provide end-to-end network clock synchronisation. This is not the same as the synchronisation used within a PSTN network or within a TDM carrier structure. The parts of an ATM network that need to be synchronised are external input and output interfaces. An ATM network does not necessarily support global clock distribution. Data transfer within the ATM network itself is asynchronous.
In ATM, traffic types that require this level of synchronisation are the Constant Bit Rate (CBR) service, voice, video, and multi-media.
A problem facing network designers is that in the absence of global clock distribution it is not possible to manufacture timing sources, other than extremely expensive atomic clocks, that provide highly accurate timing. Crystal controlled oscillators are used in most communications equipment and they are generally accurate to about fifty to one hundred parts in a million. This is not accurate enough to maintain synchronisation.
In PSTN telephone networks, extreme care is taken to synchronise the entire network to the same clock. Atomic clocks are situated at critical points within the network and timing is then propagated throughout the network along with the data. In contrast, in an ATM network, cell streams are not particularly time sensitive. Provided links are of sufficient capacity, there is no requirement in ATM to synchronise links between ATM switches. In ATM, it is only at external interfaces which are bit rate sensitive where there is a need to synchronise the data streams.
Clock synchronisation is a particular problem in the case of a connection of a PSTN telephone call across an ATM network and also in the case of two external interfaces attached to an ATM network which try to establish an 8 KHz telephone call.
SUMMARY OF THE INVENTION
In the present application, the term “cell” is used to define a fixed length data packet.
According to a first aspect of the present invention, a network interface device for an asynchronous cell switched communication network comprises:
a data input;
a memory for buffering data received at the data input; and,
means for generating a clock signal having a frequency which is controlled in accordance with a fill level of the buffer memory, wherein the clock signal is used to control a rate of transfer of data from the buffer memory.
According to a second aspect of the present invention, in a network interface device for an asynchronous cell switched communication network, a method of generating a clock signal for handling data received at an input port buffer comprises the steps of monitoring a fill level of the buffer and generating a clock signal having a frequency which is varied in accordance with the fill level of the buffer, wherein the clock signal frequency is increased when the buffer fill level exceeds a predetermined fill level and the clock signal frequency is decreased when the buffer fill level drops below the predetermined fill level.
In the present invention, data received at a network interface device is consumed by a buffer, typically a FIFO device. When the buffer fill level exceeds a predetermined level, the clock signal frequency is increased and conversely, when the buffer fill level drops below the predetermined level, the clock signal frequency is decreased.
Preferably, the means for generating the clock signal comprises a counter which is controlled by a local clock source operating at a predetermined frequency.
Preferably, the counter is preloaded with a count value which is counted by the local clock until the counter overflows whereupon an overflow signal is generated which is used as the clock signal to control the rate at which data is consumed from the buffer memory. The counter is then reloaded so that the counter restarts.
Preferably, the network interface device further comprises a means to control a mark-space ratio of the clock signal.
Preferably, the buffer memory is initially set up so that it is substantially at the predetermined fill level. As the system runs, any difference between the local clock and the rate of data received at the buffer will be shown at the buffer fill level. Preferably, the count value is adjusted by a predetermined amount to control any mismatch. In particular, in the case of a down counter, if the buffer fill level is increasing, the preloaded count value is decreased by a predetermined value to increase the frequency of the clock signal. Conversely, if the buffer fill level is decreasing, the preloaded count value is increased to decrease the frequency of the clock signal.
Preferably, the clock signal is also used to control the transmission rate of data from a data output and an associated data output buffer.
Preferably, the asynchronous cell switched communication system is an ATM network.


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