Clock sync latch circuit

Details Clock sync latch circuit Clock sync latch circuit

1998-07-01

1999-11-23

Nelms, David

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

36518905, 365233, G11C 800

Patent

active

059912278

ABSTRACT:
The present invention discloses a latch circuit used when latching an address signal or a control signal of a semiconductor memory device. In particular, the present invention discloses a clock sync latch circuit which is separately implemented to input two input signals having opposite polarities so that respective outputs corresponding to the two inputs can be outputted from each of the rising and falling edges of one clock signal. Therefore, though a skew occurs when a memory chip operates at high frequency, the number of collision between the data according to the clock signal can be prevented since it is synchronized by the same clock signal, thus preventing a malfunction of the memory chip. Also, it can obtain a large margin in the design area since only a single latch circuit can be employed.

REFERENCES:
patent: 4797574 (1989-01-01), Okubo et al.
patent: 4916670 (1990-04-01), Suzuki et al.
patent: 5191239 (1993-03-01), Rogers
patent: 5321399 (1994-06-01), Notani et al.
patent: 5619157 (1997-04-01), Kumata et al.
patent: 5726950 (1998-03-01), Okamoto et al.
patent: 5781499 (1998-07-01), Koshikawa
patent: 5856941 (1999-01-01), Keyse et al.

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