Multiplex communications – Data flow congestion prevention or control – Control of data admission to the network
Reexamination Certificate
2000-10-24
2004-10-12
Pezzlo, John (Department: 2662)
Multiplex communications
Data flow congestion prevention or control
Control of data admission to the network
C370S252000, C370S419000, C340S003300, C714S047300
Reexamination Certificate
active
06804197
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention is related to the field of network probes, and in particular, to network probe circuitry that switches between multiple clock signals to access a memory.
2. Statement of the Problem
Packet communications systems are experiencing dramatic growth in both speed and complexity. The primary engines of a packet network are the packet switches that form the nodes of the network. Packet switches are complex and expensive systems that actively process packet traffic for routing, billing, and network management. Packet switches typically require highly trained technical personnel to operate, and require fixed installations with environmentally-controlled floor space. Because of their size, cost, and complexity, packet switches may not represent the best system to monitor network performance.
Network probes are special purpose devices that have been developed to perform network monitoring external to the packet switches. Probes passively copy packet traffic from a network line and process the traffic to generate network performance statistics. Network probes offer several advantages over packet switch based solutions with respect to network monitoring. Probes are much cheaper and less complex than the typical packet switch. Probes can be positioned at a variety of network locations much easier than packet switches. Probes process copies of the packets, but do not need to actively process the packets that are received by the end users. In addition, probes are independent from the switches and may provide a more valid monitoring platform.
Network probes have used pre-configured circuitry to process traffic. Unfortunately, the pre-configured circuitry does not provide the programmability and data storage that is desired for today's rapidly changing multi-service packet networks. Network probes have also used general-purpose software processing to process traffic, but unfortunately, the increasing network speeds overwhelm competitively priced processors. Thus, network probe developers are faced with challenge of designing a network probe that is relatively cheap and simple to use, but has increased programmability and processing capacity.
Current network probe circuitry contains memory that is accessed by multiple processing systems. Often these processing systems operate at different clock rates. Consequently, the memory must be able to interface with the processing systems having the different clock rates. One solution to this problem is to operate the memory at a fixed clock rate and buffer data coming into the memory from the different processing systems. Some problems with using buffers are they are small, expensive, and slow down the access time to the memory. Another problem is that smaller buffers cannot handle large data bursts from the processing systems.
SUMMARY OF THE SOLUTION
The invention helps to solve the above problems with network probe circuitry that has a memory controller to switch clock signals transferred to a memory. The memory controller is advantageously faster than using a buffer and can handle large data bursts.
The network probe circuitry is comprised of a host interface system, a line interface system, a memory controller, and a memory. The line interface system copies packets from a network line to generate a data flow. The line interface system stores the data flow in the memory based on a first clock signal. The host interface system retrieves the data flow from the memory based on a second clock signal. The host interface system generates network performance statistics from the data flow. The memory controller receives the first clock signal and the second clock signal and selects one of the signals based on which of the interface systems has access to the memory. The memory controller transfers the selected clock signal to the memory.
REFERENCES:
patent: 6122681 (2000-09-01), Aditya et al.
patent: 6163270 (2000-12-01), Silverman
patent: 6243829 (2001-06-01), Chan
patent: 2002/0105911 (2002-08-01), Pruthi et al.
Beeston Rodney Ray
Henry Tim Warren
Agilent Technologie,s Inc.
Elallam Ahmed
Pezzlo John
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