Clock switching circuit

Details Clock switching circuit Clock switching circuit

2003-07-15

2004-10-05

Nguyen, Minh (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S099000

Reexamination Certificate

active

06801074

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a clock switching circuit for switching a clock signal to be output from a first clock signal to a second clock signal in accordance with a selection signal when outputting a first clock signal selected from a plurality of clock signals.
2. Description of the Related Art
A power consumption of an LSI is proportional to a frequency of a clock signal for operating the LSI. Thus, there is known a method of switching the clock frequency in accordance with an operation condition of the LSI, such as switching to a clock having a lower frequency when a load on the LSI is small.
FIGS. 8A
to
8
E are timing charts of a general operation in a clock switching method.
A clock signal “clkout” to be supplied to an LSI is generated by selecting one of two clock signals “clk_m” and “clk_n” having different frequencies.
FIG. 8A
is a waveform of the clock signal “clk_m”,
FIG. 8B
is a waveform of the clock signal “clk_n” and
FIG. 8E
is a waveform of the clock signal “clkout”.
FIGS. 8C and 8D
are waveforms of selection signals of the clock signals.
The clock signal “clk_m” is selected when the selection signal “sel_m” is at “H” and the clock signal “clk_n” is selected when the selection signal “sel_n” is at “H”.
Depending on a phase relationship of the clock signal and selection signal, a hazard
100
is liable to be generated as shown in FIG.
8
E. When the hazard
100
is generated, it is likely that the LSI operates erroneously, so that it is necessary that a clock switching circuit have a technique to prevent generation of a hazard.
A multi-phase clock generation circuit described in the Japanese Patent Unexamined Publication No. 2001-177510 has the PLL configuration to be controlled to have the same frequency with an operation frequency of an input data signal. Thus, a plurality of clock signals having the same frequency, a constant phase difference and different phases are output from the multi-phase clock generation circuit. Selection signals in synchronization with the plurality of clock signals are generated and the selection signals are latched by the plurality of clock signals in the selection control circuit and output to a selector for switching the clock signals. In the selector, switching of the clock signals is performed at a timing when levels of two clock signals to be switched are matched. As a result, switching of clock signals at any time without generating a hazard is realized in the technique described in the above publication.
In the technique described in the above publication, however, an oscillator for generating a reference clock signal having the same frequency with that of an input data signal is built-in in the multi-phase clock generation circuit, and a plurality of clock signals having an identical frequency and different phases are generated based on the reference clock. Accordingly, a method of switching clock signals described in the above publication cannot be applied to a plurality of clock signals having different frequencies and phases, such as a plurality of clock signals generated from a plurality of PLL circuits.
SUMMARY OF THE INVENTION
An object of the present invention is to newly provide a clock switching circuit for switching a first clock signal being output to a freely selected second clock signal among a plurality of clock signals having different frequencies and phases while preventing generation of a hazard.
To attain the above object, according to the present invention, there is provided a clock switching circuit for receiving as an input a plurality of clock signals including first and second clock signals and switching one clock signal to be output from the first clock signal to the second clock signal, comprising a plurality of unit circuits for respectively receiving as an input the clock signals, selection signals of the clock signals and enabling signals and controlling supplying and stopping of the clock signals in accordance with the selection signals and the enabling signals; and a feedback circuit for monitoring output conditions of the plurality of unit circuits and, when outputting of all clock signals of the plurality of unit circuits was stopped as a result of stopping the first clock signal, giving a plurality of the unit circuits the enabling signals for approving starting of a supply of the second clock signal.
Assuming that in accordance with a selection signal input to a unit circuit corresponding to a first clock signal, the first clock signal is output from the unit circuit. At this time, another unit circuit corresponding to a second clock signal does not output a clock signal. Next, logic states (voltage levels) of two selection signals of the two are inversed and an instruction that a clock signal to be output is switched from the first clock signal to the second clock signal is given. The unit circuit outputting the first clock signal stops outputting the first clock signal. A feedback circuit detects that the first clock signal is stopped and gives an enabling signal to the above plurality of unit circuits. A unit circuit corresponding to the second clock signal starts to supply the second clock signal due to an input of the enabling signal.


REFERENCES:
patent: 5083049 (1992-01-01), Kagey
patent: 5274678 (1993-12-01), Ferolito et al.
patent: 5289050 (1994-02-01), Ogasawara
patent: 5623223 (1997-04-01), Pasqualini
patent: 6600355 (2003-07-01), Nguyen
patent: 2003/0001612 (2003-01-01), Menezes et al.

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