Patent
1997-07-08
1999-02-09
Heckler, Thomas M.
G06F 110
Patent
active
058705953
ABSTRACT:
A clock-supply control system has an AND circuit whereby, when a transfer halt signal and a processing completion signal output by a DSP as well as a transfer halt signal output by a data output unit are all activated, the supply of a clock signal to the DSP is cut off.
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patent: 5546568 (1996-08-01), Bland et al.
patent: 5754883 (1998-05-01), Lim et al.
patent: 5765003 (1998-06-01), MacDonald et al.
Heckler Thomas M.
Mitsubishi Denki & Kabushiki Kaisha
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