Clock supply circuit layout in a circuit area

Details Clock supply circuit layout in a circuit area Clock supply circuit layout in a circuit area

1992-08-21

1993-12-14

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3074651, 307303, 307269, H03K 1901, H03K 513

Patent

active

052705927

ABSTRACT:
A clock supply circuit having a circuit area includes an input terminal for receiving a clock pulse and a buffer having an input electrically connected to the input terminal and an output. The buffer is disposed in the center of the circuit area. The clock supply circuit also includes a main conductive pattern electrically connected to the output of the buffer. The main conductive pattern is disposed through the center of the circuit area. Each of the branch conductive patterns is electrically connected to the main conductive pattern and extends from the main conductive pattern. Also, each of the branch conductive patterns has a width smaller than the width of the main conductive pattern. Each of the clock receiving circuits is electrically connected to one of the branch conductive patterns and disposed in the circuit area. The number of the clock receiving circuits electrically connected to one branch conductive pattern is same.

REFERENCES:
patent: 4769558 (1988-09-01), Bach
patent: 4812684 (1989-03-01), Yamagiwa et al.
patent: 4851717 (1989-07-01), Yabe
patent: 4857765 (1989-08-01), Cahill et al.
patent: 5012427 (1991-04-01), Kuribayashi
patent: 5029279 (1991-07-01), Sasaki et al.
patent: 5164817 (1992-11-01), Eisenstadt et al.
patent: 5172330 (1992-12-01), Wantanabe et al.

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