Clock supply circuit having adjustment capacitance

Details Clock supply circuit having adjustment capacitance Clock supply circuit having adjustment capacitance

1989-08-17

1991-05-07

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307481, 307591, 307246, H07K 1714

Patent

active

050139428

ABSTRACT:
Disclosed is a clock supply circuit operating in a first phase and a second phase. Each buffer provided in each channel operating in the second phase has the same drive ability, and the number of flip-flops which are dependent on each buffer is the same. When the number of the flip-flops is not the same, capacitance means is provided in each channel in order to make conditions uniform for operation in the second phase.

REFERENCES:
patent: 4639615 (1987-01-01), Lee et al.
patent: 4661721 (1987-04-01), Ushiku
patent: 4692633 (1987-09-01), Ngai et al.
patent: 4812684 (1989-03-01), Yamagiwa et al.
patent: 4851717 (1989-07-01), Yabe
patent: 4868425 (1989-09-01), Lindenfelsen
Eby G. Friedman, "Design and Analysis of a Hierarchical Clock Distribution System for Synchronous Standard Cell/Macrocell VLSI", IEEE Journal of Solid State Circuits, SC-21 (1986) Apr. No. 2, New York, U.S.A., pp. 240-246.

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