Clock sources and methods with reduced clock jitter

Details Clock sources and methods with reduced clock jitter Clock sources and methods with reduced clock jitter

2007-02-06

2007-02-06

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S294000, C327S551000

Reexamination Certificate

active

11078272

ABSTRACT:
Clock sources are provided which are especially useful for reducing phase noise in signal samplers that typically provide samples of an analog input signal in signal-conditioning systems such as analog-to-digital converters. This phase noise reduction is realized with the recognition that sampler noise is related to clock jitter by a ratio of the input signal's slew rate to the clock's slew rate. Clock embodiments include a frequency divider and a signal gate. The divider divides a first signal to provide a second signal with a slew rate lowered from the slew rate of the first signal and the gate passes the second signal when commanded by the first signal to thereby generate a clock signal.

REFERENCES:
patent: 4389728 (1983-06-01), Tsuzuki
patent: 5168551 (1992-12-01), Jeong
patent: 6008691 (1999-12-01), Morita
patent: 6122326 (2000-09-01), Jackson et al.
patent: 6130564 (2000-10-01), Wang
patent: 6163182 (2000-12-01), Canard et al.
patent: 6229357 (2001-05-01), Nair et al.
patent: 6232905 (2001-05-01), Smith et al.
patent: 6356129 (2002-03-01), O'Brien et al.
patent: 6396429 (2002-05-01), Singer et al.
patent: 6580383 (2003-06-01), Devendorf et al.
patent: 6650263 (2003-11-01), Dillon
patent: 6734748 (2004-05-01), Livezey
patent: 6816021 (2004-11-01), Hahn et al.
patent: 6842054 (2005-01-01), Wang
Smith, Paul, “Little Known Characteristics of Phase Noise”, www.rfdesign.com, Mar. 2004, pp. 46-52.
Sin, Sai-Weng, “Quantitative Noise Analysis of Jitter-Induced Nonuniformly Sampled-and-Held Signals”, Faculty of Science and Technology, University of Macau, Macau, China, 4 pages, published Apr. 2003.
Goldberf, Bar-Giora, “The Effects of Clock Jitter on Data Conversion Devices”, www.rfdesign.com, Aug. 2002, pp. 26-32.
“Design a Low-Jitter Clock for High-Speed Data Converters”, Maxim, Dallas Semiconductor, Nov. 20, 2001, 14 pages.

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