Clock source with automatic duty cycle correction

Details Clock source with automatic duty cycle correction Clock source with automatic duty cycle correction

1983-07-11

1985-07-02

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307234, 307269, 328 58, 328111, 331183, H03L 100, H03K 303, H03K 526

Patent

active

045270759

ABSTRACT:
A clock source for timing and synchronizing the operation of digital data processing equipment and having automatic duty cycle correction is described. A source of signals provides clock signals at a predetermined frequency. A buffer circuit provides the true and complement clock signals to low pass filters that function to filter the true and complement clock signals to DC levels proportional to the duty cycle of the source signals. The DC voltages represent instantaneous deviation voltages from a known reference and are applied to a differential amplifier circuit for providing a feedback signal for adjusting the duty cycle of the clock output pulses that are available. One embodiment has the source of signals directly coupled to the buffer circuitry and utilizes the feedback signal to adjust the duty cycle of the signal source circuitry. A second embodiment has the source signals capacitively coupled to the self-correcting circuitry and the feedback signals adjust the duty cycle of the clock output signal.

REFERENCES:
patent: 3721835 (1973-03-01), Hess
patent: 3979693 (1976-09-01), Saari
patent: 4034236 (1977-07-01), Aveneau et al.
patent: 4038611 (1977-07-01), Greig
patent: 4149179 (1979-04-01), Wilcox
patent: 4277697 (1981-07-01), Hall et al.
patent: 4439689 (1984-03-01), Chazenfus
patent: 4461962 (1984-07-01), Hacke et al.
patent: 4479216 (1984-10-01), Krambeck et al.
Niccore, "Phase-Lock Loop With Constant Duty Cycle", IBM Tech. Disc. Bull. vol. 14, No. 6, Nov. 1971 pp. 1838-1839.

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