Clock skew tolerant clocking scheme

Details Clock skew tolerant clocking scheme Clock skew tolerant clocking scheme

2005-06-28

2005-06-28

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Regenerating or restoring rectangular or pulse waveform

C327S141000, C327S166000

Reexamination Certificate

active

06911854

ABSTRACT:
A clock skew tolerant clocking scheme addresses both the max-time and min-time problems by using dual transparent pulsed latches operated by complementary phases of the clock signal. According to the present invention, the first pulsed latch is triggered by a first pulse derived by the leading edge of a clock signal pulse and the second pulsed latch is triggered by a second pulse derived from the trailing edge of the clock signal. By employing transparent pulse latches, the clock skew tolerant clocking scheme of the invention provides max-time clock skew tolerance. In addition, unlike prior art solutions, according to the invention, the transparency periods of the dual complementary pulsed latches do not overlap so there is never a transparency period between two successive stages and, therefore, there is no opportunity to introduce the min-time, or racing condition, problem.

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