Clock skew removal apparatus

Details Clock skew removal apparatus Clock skew removal apparatus

2000-01-27

2001-11-20

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S159000, C327S161000, C327S271000, C375S373000, C331SDIG002

Reexamination Certificate

active

06320436

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to circuitry for synchronising clock signals and in particular to a self-adjusting delay line which provides a balancing delay in one clock signal to match an unknown delay in the other signal so that the first and second clock signals can be synchronised and thereby the skew between the two signals may preferably be removed.
As the clock speed for integrated circuits increases, external interfaces are becoming proportionally slower compared to the internal circuitry, and synchronisation of interfaces with internal logic becomes more critical.
Clock skew removal techniques are necessary in applications such as frame buffer interfaces because memory timing requirements cannot be guaranteed to be met under all conditions and across process corners if fixed delays are used.
In the past the most common approach to clock deskew has been to use a phase locked loop (PLL). This is a different type of circuit to a self-adjusting delay line and achieves phase alignment by frequency adjustment of a voltage controlled oscillator. A PLL also needs to detect frequency differences in addition to phase differences.
However use of a PLL to effect skew removal has three main drawbacks. Firstly the provision of a PLL has special requirements regarding layout of the circuitry since the PLL is large. Secondly if the clock frequency changes suddenly it will not deskew correctly whilst it settles and may even output a different number of clock pulses during that period. Thirdly, it is difficult to write a functional model of a PLL which is cycle-accurate in system simulations.
It is therefore an object of the present invention to at least partly mitigate the above problems.
SUMMARY OF THE INVENTION
According to the present invention there is provided a digital clock deskew apparatus for synchronising the phase of a first clock signal, with the phase of a second clock signal which includes an unknown phase delay, said deskew apparatus comprising a tapped delay line connected to receive said first clock signal and comprising a plurality of delay elements each applying a respective delay to said first clock signal and outputting a respective delayed clock signal, selector apparatus for selecting one of the delayed clock signals in response to a control signal, and phase detector apparatus for comparing the phase of the selected delayed clock signal with the phase of said second clock signal and outputting the control signal to control selection of the delayed clock signal having a predetermined phase relationship with the phase of the second clock signal to thereby accommodate for the unknown phase delay.
Preferably said selector apparatus comprises a digital clock deskew apparatus wherein said selector apparatus comprises counter logic for receiving said control signal and having a clock input terminal which receives the selected delayed clock signal to thereby clock the counter, whereby the counter provides a count signal indicating a respective delayed clock signal which is to be selected.
Advantageously said selector apparatus further comprises a multiplexer having a control input connected to receive the count signal from said counter and a plurality of delay inputs each receiving an associated one of said respective delayed clock signals output from the delay elements in said delay line, whereby the multiplexer controls which of said delay inputs is connected to a multiplexer output to thereby output said selected delayed clock signal.
Conveniently said multiplexer further comprises a first input connected to receive said first clock signal and controls which of said first input or said delay inputs is connected to the multiplexer output.


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