Clock skew reduction

Details Clock skew reduction Clock skew reduction

1996-06-21

1999-06-22

Tu, Trinh L.

Excavating

395552, 395558, G06K 504, G06F 112, G06F 104

Patent

active

059149639

ABSTRACT:
A computer system has a skew compensation circuit for synchronizing the phase of a first periodic signal in one device with a second periodic signal in a second device connected to the first device by a connection that imposes a propagation delay. The skew compensation circuit has a receiver connected to receive the second periodic signal delayed by the propagation delay and circuitry for providing a delay signal representative of the propagation delay. The skew compensation circuit further includes a generator connected to generate the first periodic signal in phase with the second periodic signal based on the first periodic signal and the delay signal.

REFERENCES:
patent: 5087829 (1992-02-01), Ishibashi et al.
patent: 5398262 (1995-03-01), Ahuja
patent: 5448193 (1995-09-01), Baumert et al.
patent: 5463337 (1995-10-01), Leonowich
patent: 5467040 (1995-11-01), Nelson et al.
patent: 5486783 (1996-01-01), Baumert et al.
patent: 5631591 (1997-05-01), Bar-Niv
patent: 5661425 (1997-08-01), Minoda et al.

Affiliated with

Also associated with

Rating

Clock skew reduction does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Clock skew reduction, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock skew reduction will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1712976