Clock skew minimization and method for integrated circuits

Details Clock skew minimization and method for integrated circuits Clock skew minimization and method for integrated circuits

1997-10-20

2000-03-21

Niebling, John F.

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

438108, 438455, H01L 2144, H01L 2148, H01L 2150, H01L 2130, H01L 2146

Patent

active

060402032

ABSTRACT:
A precise and highly controllable clock-distribution network is provided on one active substrate to distribute clock signals with minimal skew to another active substrate by connecting the substrates together face-to-face using flip-chip technology. Since the clock-distribution substrate is sparse, "quiet busses" are provided on the sparse substrate to facilitate the high-speed transfer of data over relatively long distances. Low-power devices (e.g., DRAM) can be provided on one substrate for use by higher-power logic (e.g., a processor) on another substrate with minimal interconnection distance.

REFERENCES:
patent: 4755704 (1988-07-01), Flora et al.

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