Clock skew measurement technique

Horology: time measuring systems or devices – Time interval – Electrical or electromechanical

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Details

324158R, 371 221, G04F 800, G01R 3102, G01R 1512

Patent

active

052355667

ABSTRACT:
Method and apparatus are disclosed for measuring the clock offset between a reference latch point and a subject latch point in a system. In the system, an associated latch point is provided on each chip which has a subject latch point, the clock offset to which is to be measured. Test data distribution means is provided for distributing a test data signal from a test data source point to the data input of the reference latch point and to the data input of the associated latch point. Cross-transmission means are also provided for connecting together the data input of the reference latch point and the data input of the associated latch point. A pulse burst generator is connected to the clock source point in the system and a test data signal generator is connected to the test data signal source point. The test data signal generator responds to each burst of clock pulses by generating a logic level transition on the test data source point at a presettable time following a known one of the edges of the clock pulses in each burst. By adjusting the presettable delay in the test data signal generator, and observing the output of a given latch point after the last clock pulse in each burst reaches the clock input of the given latch point, a delay setting is determined at which the path delay for the following two paths are approximately equivalent: (1) the path from the clock source point through the clock distribution means to the clock input of the given latch point; and (2) the path from the clock source point through the test data signal generator, through the test data distribution means and to the data input of the given latch point.

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