Clock skew correction arrangement

Details Clock skew correction arrangement Clock skew correction arrangement

1988-02-26

1989-06-13

Griffin, Robert L.

Pulse or digital communications

Spread spectrum

Direct sequence

371 1, 371 61, H04L 706

Patent

active

048399078

ABSTRACT:
A skew compensation circuit removes skew between a data stream and the clock of a processing module to which the data stream clocked at the same frequency is applied. A delayed data stream is generated. Either the data stream or the delayed data stream is selected to be clocked in the processing module. The selected data stream and a delayed version of the selected data stream are compared at prescribed transitions of the processing module clock to detect differences between the state of the selected data stream signal at the clock transition and the state of the delayed selected data signal. In the event of a detected difference in states, the other of the input data stream and the delayed data stream is selected for clocking in the processing module.

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patent: 4677618 (1987-06-01), Haas et al.
patent: 4682342 (1987-07-01), Vetani

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