Clock skew circuit

Details Clock skew circuit Clock skew circuit

1998-02-25

2000-04-11

Le, Dinh T.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

327291, 327271, 327259, 327261, H03K 386

Patent

active

060492414

ABSTRACT:
A clock circuit including an input terminal (300) for receiving a clock signal and a first pulse generator (302) coupled to the input terminal. The first pulse generator is operable to generate a voltage pulse in response to a logic-low voltage to logic-high voltage transition of the clock signal. The circuit also includes a second pulse generator (304) coupled to the input terminal, the second pulse generator being operable to generate a voltage pulse in response to a logic-high voltage to logic-low voltage transition of the clock signal. A first clock deskewing circuit (306) is coupled between the first pulse generator and a first clock signal output terminal and a second clock deskewing circuit (308) is coupled between the second pulse generator and a second clock signal output terminal. The circuit may also include an OR logic circuit (310) coupled to the first and second clock signal output terminals, and a third pulse generator (312) coupled to the OR logic circuit, the third pulse generator having a third clock signal output terminal (314).

REFERENCES:
patent: 4943787 (1990-07-01), Swapp
patent: 5389831 (1995-02-01), Eisenstadt

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