Clock skew avoidance technique for pipeline processors

Details Clock skew avoidance technique for pipeline processors Clock skew avoidance technique for pipeline processors

1989-08-03

1990-08-14

Shaw, Gareth D.

Boots, shoes, and leggings

371 1, 3642318, 364271, 364239, 36423951, 364247, 364260, 3642602, 364259, 3642595, G06F 1300

Patent

active

049492497

ABSTRACT:
A technique for providing skew compensation particularly in association with a pipelined processor. The skew occurs between first and second clock signals. The skew compensation technique of the invention provides for the proper transfer of information between stages even though the clock signals may have a skew greater than the inter-stage delay. A holding or latching means is provided between stages so as to hold the previous stage data for clocking into the subsequent stage register.

REFERENCES:
patent: 3753241 (1973-08-01), Bayne
patent: 4229790 (1980-10-01), Gilliland et al.
patent: 4392200 (1983-07-01), Arulpragasam et al.
patent: 4566062 (1986-01-01), Ohnishi et al.
patent: 4809162 (1989-02-01), Si
patent: 4811364 (1989-03-01), Sager et al.

Affiliated with

Also associated with

Rating

Clock skew avoidance technique for pipeline processors does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Clock skew avoidance technique for pipeline processors, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock skew avoidance technique for pipeline processors will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-467274