Clock signal switching circuit

Details Clock signal switching circuit Clock signal switching circuit

2001-05-15

2002-06-25

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

Having selection between plural continuous waveforms

C327S166000, C327S298000, C327S407000

Reexamination Certificate

active

06411135

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a clock signal switching circuit and, more specifically, to a clock signal switching circuit that can switch between clock signals without generating noise such as a hazard.
2. Description of the Related Art
FIG. 6
shows a circuit diagram of a clock signal switching circuit
100
in a related art. The clock signal switching circuit
100
includes a two-input and one-output selector
1
wherein two kinds of clock signals CK
1
(a first signal) and CK
2
(a second clock signal), each of which has a unique clock signal form, are provided at its input terminals. The output of the selector
1
is connected to an input terminal of a driver
2
. The selector
1
selects one of the first and second clock signals CK
1
and CK
2
according to the logic level of a selection signal SL, and generates the selected signal. The driver
2
activates the selected signal, and generates the activated signal as the clocked signal CKo.
FIG. 7
is a signal timing chart showing the operation of the clock signal switching circuit
100
illustrated in FIG.
6
. As described above, the first and second clock signals CK
1
and CK
2
are provided to the selector
1
. When a section signal SL at an L level (a second logic level), is applied to the selector
1
, the first clock signal CK
1
is selected. When a section signal SL at an H level (a first logic level), is applied to the selector
1
, the second clock signal CK
2
is selected. Then, the selected signal is provided to the driver
2
to be activated therein. After activating the selected signal, the clocked signal CKo is generated from the driver
2
. As further described above, the clock signal switching circuit
100
illustrated in
FIG. 6
switches between the first and second clock signals CK
1
and CK
2
by the selector
1
according to the logic level of the selection signal SL, and activates the selected signal CK
1
or CK
2
by the driver
2
.
However, since the phases of the first and second clock signals CK
1
and CK
2
are different, noise such as a hazard hd, which is shown in
FIG. 7
, appears on the clocked signal CKo when the first and second clock signals are switched according to the logic level of the selection signal SL. When the hazard appears on the clocked signal CKo, the hazard may be a trigger for malfunctioning of all circuits, which are controlled by the clocked signal CKo.
SUMMARY OF THE INVENTION
It is therefore an objective of the invention to resolve the above-described problem and to provide a clock signal switching circuit that provides a clocked signal without generating any hazards when the clock signals are switched.
The objective is achieved by a clock signal switching circuit, which receives at least two clock signals having a phase difference between them, and an original signal for switching between the clock signals, and generates an output signal by selecting one of them. The clock signal switching circuit includes a detection circuit receiving the original signal, the detection signal forming a detection signal when a transition between a first and a second logic level of the original signal is received, a delay circuit receiving the original signal and the detection signal, the delay circuit passing through the original signal when the original signal maintains its logic level, and the delay circuit outputting a selection signal when the detection circuit receives the detection signal, a first selector receiving the clock signals, selecting one of the clock signals according to the logic level of the selection signal, and outputting a first selected signal, a second selector receiving a first control signal and a second control signal, selecting one of the control signals according to the logic level of the selection signal, and outputting a second selected signal, the first control signal changing in response to one of the clock signals and the detection signal, and the logic level of the second control signal changing in response to the other clock signal and the detection signal, and a gate circuit receiving the first and second selected signal, generating the output signal wherein the logic level of the selection signal is changed by the delay circuit after the logic level of both of the first and second control signals has changed.
Further, the objective is achieved by a clock signal switching circuit that receives two clock signals having a phase difference between them, and a selection signal for switching between the clock signals, and generates an output signal by switching between the clock signals according to the logic level of a switch signal. The clock signal switching circuit includes a first output control circuit receiving the selection signal and the first clock signal, the first output control circuit outputting a first signal having a fixed logic level in synchronism with the raising transition of the first clock signal when the selection signal is at a first logic level, and the first output control circuit outputting the first signal, which is the same as the first clock signal, when the selection signal is at a second logic level, maintaining the first signal which is the same as the first clock signal for a particular period staring when the logic level of the selection signal is change and ending when the first clock signal goes up, a second output control circuit receiving the selection signal and the second clock signal, the second output control circuit outputting a second signal, which is the same as the second clock signal, in synchronism with the raising transition of the second clock signal when the selection signal is at a first logic level, and the second output control circuit outputting the second signal having a fixed logic level when the selection signal is at a second logic level, and, maintaining the second signal having the fixed logic level for a particular period staring when the logic level of the selection signal is change and ending when the second clock signal goes up, a switch signal generating circuit, which receives the first and second clock signals and the selection signal, generating a switch signal, the switch signal generating circuit outputting the switch signal in response to the transition of the logic level of either the first or the second clock signal after the logic level of the selection signal is changed, and a selector selecting and outputting one of the first and second signal according to the logic level of the switch signal as the output signal.


REFERENCES:
patent: 5274678 (1993-12-01), Ferolito et al.
patent: 5315181 (1994-05-01), Schowe
patent: 5502409 (1996-03-01), Schnizlein et al.
patent: 6239626 (2001-05-01), Chesavage

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