Clock signal supplying apparatus

Details Clock signal supplying apparatus Clock signal supplying apparatus

1997-08-06

2001-06-12

Marcelo, Melvin (Department: 2663)

Multiplex communications

Communication techniques for information carried in plural...

Combining or distributing information via time channels

Reexamination Certificate

active

06246700

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a clock signal supplying apparatus and particularly, a clock signal supplying apparatus for supplying a clock signal to a plurality of functional blocks in a serial data processing switch system such as a switchboard in asynchronous transfer mode communications (referred to as ATM hereinafter).
As the frequency of a clock signal for electronic devices has sharply been increased for carrying out high-quality high-speed processing, its relevant problems arise including fault action of an electronic device due to clock noise and increase of power consumption For attenuating the noise or minimizing the power consumption, a clock signal control technique is employed in which the functional blocks in an electronic apparatus are supplied with clock signals only when they are carrying out logic operations.
For example, a logic circuit driving apparatus for supplying a clock signal at timing with the action of a functional block is depicted in Japanese Patent Laid-open Publication No. H4-302014. The logic circuit driving apparatus includes functional blocks
1
,
2
, and
3
for carrying out a series of logic operations, as shown in FIG.
4
. The functional block
1
is supplied with an action data signal
4
a,
starts performing an operation, and delivers an action data signal
4
b
during the operation. The functional block
2
is responsive to the action data signal
4
b
for starting a logic operation and releases an action data signal
4
c
during the logic operation. The action data signal
4
c
is then supplied to the functional block
3
which in turn starts its logic operation.
The logic circuit driving apparatus also includes a sequence controller
5
to which status data signals
6
a,
6
b,
and
6
c
are fed from their respective functional blocks
1
,
2
, and
3
. Also, a master clock signal
7
is supplied to the sequence controller 5. In response to the status data signals
6
a,
6
b,
and
6
c,
the sequence controller
5
produces and delivers action signals
8
a,
8
b,
and
8
c,
each consisting of a clock signal CLK and other signals, to the functional blocks
1
,
2
, and
3
respectively. The functional blocks
1
,
2
, and
3
are also loaded with a common reset signal 9.
In action, when the action data signal
4
a
is not supplied to the logic circuit driving apparatus, the functional block
1
remains disabled releasing none of the action data signal
4
b
and the status data signal
6
a.
Accordingly, the functional block
1
is disabled to receive the action signal
8
a
thus the clock signal CLK from the sequence controller
5
. Equally, the functional blocks
2
and
3
are not supplied with the action data signals
4
b
and
4
c
and thus receive none of the clock signal CLK.
Upon receiving the action data signal
4
a
, the functional block
1
starts with delivering the status data signal
6
a
to the sequence controller
5
. The sequence controller
5
in response to the status data signal
6
a
releases the action signal
8
a
to the functional block
1
. The functional block
1
receives the clock signal CLK in the action signal
8
a
and then performs its logic operation. During the logic operation, the functional block
1
delivers the action data signal
4
b
to the functional block
2
. Upon receiving the action data signal
4
b,
the functional block
2
starts with the same action as of the functional block
1
.
In this manner, the functional blocks
1
and
2
supply the succeeding functional blocks
2
and
3
with their respective action data signals
4
b
and
4
c
. The functional blocks
1
,
2
, and
3
excited by the action data signals
4
a
,
4
b
, and
4
c
respectively deliver their respective status data signals
6
a,
6
b,
and
6
c
to the sequence controller
5
and in turn receive the clock signal CLK from the sequence controller
5
for performing their logic operations.
Such a conventional logic circuit driving apparatus has a disadvantage to be solved. Since the functional block
1
to
3
start operating only when they have been loaded with the action data signals
4
a
to
4
c,
they have to be programmed to operate in a time sequence and thus, are hardly suited for any applicable system.
For example, in a specific system such as an ATM switchboard which has to carry out actions in response to received data without using the action data signal
4
a,
the functional blocks are activated in different orders depending on the received data. The prescribed conventional logic circuit driving apparatus may hardly be utilized for effective control of the clock signal.
SUMMARY OF THE INVENTION
It is a primary object of the present invention to provide a novel, improved clock signal supplying apparatus appropriated for use in a system in which functional blocks are not programmed to operate in a time sequence.
It is another object of the present invention to provide a novel, improved clock signal supplying apparatus for controlling the supply of clock signal in accordance with data to be processed.
It is a further object of the present invention to provide a novel, improved clock signal supplying apparatus for supplying a clock signal to a functional block only when requested thus to eliminate noise from unwanted clock signal and minimize power consumption.
For achievement of the object, the clock signal generating apparatus incorporates a plurality of clock signal generating circuits for receiving an input data of serial mode having at its front an indicator bit indicating that the input data is eligible or not, and supplying clock signals to corresponding functional blocks which are responsive to their respective clock signals for performing logic operations.
The clock signal supplying circuit comprises: a status generating means for receiving the input data assigned to the corresponding functional block along with a sync signal indicative of start timing of the input data, and when it is judged from the indicator bit that the input data is eligible, enabling a status signal for a period required for carrying out the logic operation of the functional block; and a clock controlling means for supplying a master clock signal, which is commonly supplied to the clock signal supplying circuits, as the clock signal to the corresponding functional block while the status signal is being enabled.
The clock signal generating apparatus of the present invention having such an arrangement can be operated in the following manner.
While one of the functional blocks is loaded with e. g. a known cell input data employed in an known ATM communications network, the clock signal supplying circuit assigned to the functional block also receives the cell input data. Simultaneously, the clock signal generating circuit is fed with the sync signal indicative of start timing of the cell input data The status generating means of the clock signal supplying circuit examines the first or indicator bit of the call input data to determine whether the input data is eligible or not. When it is judged that the input data is eligible, the status signal is enabled for a period required for carrying out the logic operation of the functional block.
The status signal is transmitted to the clock controlling means together with the master clock signal which is commonly supplied to all the clock signal supplying circuits. While the status signal is being enabled, the master clock signal is supplied as the clock signal to the functional block.


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patent: 5117443 (1992-05-01), Shires
patent: 5331667 (1994-07-01), Izumi
patent: 5341091 (1994-08-01), Kurita
patent: 5463663 (1995-10-01), Maruyama et al.
patent: 5574753 (1996-11-01), Vartti et al.
patent: 5590116 (1996-12-01), Zhang
patent: 5752012 (1998-05-01), Smith
patent: 5844891 (1998-12-01), Cox
patent: 5859846 (1999-01-01), Kim et al.
patent: 5903570 (1999-05-01), Van Berkel
patent: 5987620 (1999-11-01), Tran
patent: 4-302014 (1992-10-01), None
patent: 5-108038A (1993-04-01), None

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