Dynamic information storage or retrieval – Binary pulse train information signal – Binary signal gain processing
Patent
1983-10-20
1987-06-09
Psitos, Aristotelis M.
Dynamic information storage or retrieval
Binary pulse train information signal
Binary signal gain processing
369 50, 360 51, G11B 502, G11B 509
Patent
active
046725970
ABSTRACT:
A clock signal reproducing circuit for a player reproducing information of a disc reproduces a clock signal from a signal reproduced from a disc via a pickup head. The clock signal reproducing circuit comprises clock signal generating circuit for generating a clock signal having a period of about 1
(n being an integer) of the signal reproduced from the disc, a first detecting circuit which, in response to the signal reproduced from the disc via the pickup head and the clock signal delivered from the clock signal generating circuit, detects a phase error between the two signals containing a component for 1/2 period of the clock signal, a second detecting circuit which, in response to the clock signal delivered from the clock signal generating circuit, detects the component for 1/2 period of the clock signal at a timing when the first detecting circuit detects the phase error, and a combinating circuit which cancels the component for 1/2 period of the clock signal by combining output signals of the first and second detecting circuits thereby to provide only the phase error component. A phase locked loop is operated in response to this phase error component such that the clock signal and the input signal reproduced from the disc are in phase with each other.
REFERENCES:
patent: 4222009 (1980-10-01), Moulton et al.
patent: 4371974 (1983-02-01), Dugan
patent: 4371975 (1983-02-01), Dugan
patent: 4380815 (1983-04-01), Clendening
patent: 4400667 (1983-08-01), Belkin
patent: 4422176 (1983-12-01), Summers
patent: 4520319 (1985-05-01), Baker
patent: 4535459 (1985-08-01), Hogge, Jr.
Nippon Gakki Seizo Kabushiki Kaisha
Psitos Aristotelis M.
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