Clock signal propagation gate and semiconductor integrated...

Details Clock signal propagation gate and semiconductor integrated... Clock signal propagation gate and semiconductor integrated...

2003-01-14

2004-04-20

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S298000, C326S095000

Reexamination Certificate

active

06724231

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit including a clock signal propagation gate. More particularly, the invention relates to techniques for reducing clock signal skew (or a time difference between clock signals arriving at respective end points) and for facilitating the delay adjustment of the clock signals.
2. Description of the Background Art
Design of a clock distribution circuit is important in synchronous pipeline design of LSI circuits. Techniques for the clock distribution circuit are mainly of two types: a single-buffer scheme and a clock-tree scheme. The clock-tree scheme can achieve reductions in power consumption and in area as compared with the single-buffer scheme, and also can easily control clock signals.
FIG. 5
is a circuit diagram of a typical clock distribution circuit of the clock-tree type. A clock signal inputted at a clock origin (or a starting point of a clock) is distributed through a buffer
200
to buffers
201
and
202
. The clock signal passed through the buffer
201
is further distributed to buffers
203
and
204
. Finally, these distributed clock signals reach sequential circuits (e.g., latches and flip-flops (FFs)) at the end points of the clock tree. Buffers
200
to
212
are shown in FIG.
5
. Sequential circuits
213
to
216
each including a plurality of flip-flops operating on the rising edge of the clock signal are shown at the end points of the clock tree.
Various structures of the clock distribution circuit of the clock-tree type have been proposed. Recently, an H-tree scheme has been proposed which can provide a uniform layout of paths from the clock origin to the sequential circuits at the end points. The H-tree scheme is disclosed in “A Clock Distribution Network for Microprocessors,” 2000 Symposium on VLSI Circuits Digest of Technical Papers.
FIG. 6
is a circuit diagram of a clock distribution circuit of the clock-tree type capable of controlling the clock signal. The clock distribution circuit of
FIG. 6
includes a control OR gate
224
and a control AND gate
226
in paths. These control gates
224
and
226
can stop feeding some or all of the clock signals to the sequential circuits at the end points. Buffers
220
to
223
,
225
, and
227
to
232
and sequential circuits
233
to
236
are shown in FIG.
6
.
A path including the control AND gate
226
will be described.
FIGS. 7A and 7B
are partial circuit diagrams of the clock distribution circuit having the control AND gate.
FIG. 7A
shows a path from the clock origin to the sequential circuit
236
at one end point in the clock distribution circuit shown in
FIG. 6. A
clock signal inputted at the clock origin propagates through the buffers
220
and
222
to the control AND gate
226
. The two-level control AND gate
226
includes an NAND gate
240
at the first level, and an inverter
245
at the second level.
FIG. 7B
is a circuit diagram of the control AND gate
226
. The NAND gate
240
at the first level includes pMOS transistors
241
,
242
and nMOS transistors
243
,
244
. The inverter
245
at the second level includes a pMOS transistor
246
and an nMOS transistor
247
.
The clock signal outputted from the control AND gate
226
propagates through buffers
228
and
232
to the sequential circuit
236
at the end point. The sequential circuit
236
shown in
FIG. 7A
is driven upon receipt of the rising edge of the clock signal.
The operation of the control AND gate
226
will be described. A control signal controls the propagation of the rising edge of the clock signal inputted to the control AND gate
226
. When the control signal is LOW, the output from the control AND gate
226
remains LOW independently of the occurrence of a rising edge (or a LOW-to-HIGH signal transition) of the input clock signal. Thus, no rising edge of the clock signal propagates when the control signal for the control AND gate
226
is LOW.
On the other hand, when the control signal is HIGH, the input clock signal is inverted by the NAND gate
240
at the first level, and is then inverted again by the inverter
245
at the second level. Thus, the rising edge of the clock signal propagates when the control signal for the control AND gate
226
is HIGH.
Next, a path including the control OR gate
224
will be described.
FIGS. 8A and 8B
are partial circuit diagrams of the clock distribution circuit having the control OR gate.
FIG. 8A
shows a path from the clock origin to the sequential circuit
233
at one end point in the clock distribution circuit shown in FIG.
6
.
FIG. 8B
is a circuit diagram of the two-level control OR gate
224
which includes a NOR gate
250
at the first level and an inverter
255
at the second level. The NOR gate
250
at the first level includes pMOS transistors
251
,
252
and nMOS transistors
253
,
254
. The inverter
255
at the second level includes a pMOS transistor
256
and an nMOS transistor
257
.
A control signal controls the propagation of the rising edge of the clock signal inputted to the control OR gate
224
. When the control signal is LOW, the input clock signal is inverted by the NOR gate
250
at the first level, and is then inverted again by the inverter
255
at the second level. Thus, the rising edge of the clock signal propagates when the control signal for the control OR gate
224
is LOW.
On the other hand, when the control signal is HIGH, the output from the control OR gate
224
remains HIGH independently of the occurrence of a rising edge of the input clock signal. Thus, no rising edge of the clock signal propagates when the control signal for the control OR gate
224
is HIGH.
In the clock distribution circuits of the clock-tree type shown in
FIGS. 5 and 6
, differences exist in length of interconnect lines, in the number of adjacent interconnect lines and in the number of gate levels, depending upon the paths from the clock origin to the sequential circuits at the end points. This produces a delay difference between clock signals, depending on the interconnect line paths, to result in a tendency toward higher clock signal skew (or a greater time difference between clock signals arriving at respective end points). Further, when the sequential circuit at the end point is driven by the rising edge of the clock signal, there is a need for the clock distribution circuit to propagate the rising edge of the clock signal.
Each of the buffers in the clock distribution circuits shown in
FIGS. 5 and 6
is a two-level buffer including two inverters
260
and
263
, as shown in FIG.
9
. The first-level inverter
260
includes a pMOS transistor
261
and an nMOS transistor
262
, and the second-level inverter
263
includes a pMOS transistor
264
and an nMOS transistor
265
. Since an interconnect line connected to the output of the buffer has a large parasitic capacitance, the pMOS transistor
264
for driving the interconnect line is designed to have a greater current-driving capability than that of the pMOS transistor
261
, and the nMOS transistor
265
is designed to have a greater current-driving capability than that of the nMOS transistor
262
. In general, the driving capability of the pMOS transistor
264
of the inverter
263
is less than that of the nMOS transistor
265
of the same inverter
263
. Thus, if the rising edge of the clock signal is applied to the buffer shown in
FIG. 9
, the propagation delay of the clock signal increases after the clock signal passes through the buffer.
To solve the higher clock signal skew problem, it is necessary to increase the driving capability of the second-level inverter
263
or, particularly, the driving capability of the pMOS transistor
264
. In other words, a solution to the problem is to increase the gate width of the pMOS transistor
264
of the second-level inverter
263
. However, this solution increases the area of the pMOS transistor
264
to accordingly increase the area of the buffer itself. This results in the increase in the area of the clock distribution circuit to give ris

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