Clock signal producing circuit immediately producing clock...

Details Clock signal producing circuit immediately producing clock... Clock signal producing circuit immediately producing clock...

2000-10-27

2003-06-10

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S094000, C327S095000, C327S291000, C327S293000, C341S200000

Reexamination Certificate

active

06577167

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to clock signal producing circuit. More particularly, the present invention relates to a clock signal producing circuit immediately producing a clock signal synchronized with an input signal and also reproducing the input signal.
2. Description of the Related Art
A clock signal producing circuit, which produces a clock signal synchronizing with an input signal, is needed in a communication system.
Such a clock signal producing circuit is known in Japanese Laid Open Patent Application (JP-A-Heisei, 9-149018). As shown in
FIG. 1
, the known clock signal producing circuit includes a timing judging circuit
101
, a selector controlling circuit
102
, a selector
103
, a reset voltage control oscillator (hereafter, referred to as a reset VCO circuit)
104
, and a multiplication PLL circuit (Phase Lock Loop circuit)
105
.
The timing judgment circuit
101
judges whether a phase is advanced or delayed as compared with a clock signal, and outputs the judged result to the selector controller
102
. The selector controller
102
feeds back a phase control signal through the selector
103
to the reset VCO circuit
104
.
The reset VCO circuit
104
generates a clock signal having a phase corresponding to the phase control signal received through the selector
103
and a frequency corresponding to a frequency control signal from the multiplacation PLL circuit
105
. The clock signal generated by the reset VCO circuit
104
is used in the data communication and the like.
The known clock identification reproduction circuit detects whether the phase is advanced or delayed, and performs a feedback control on the reset VCO circuit
104
. However, a certain time is required until the reset VCO
104
on which the feedback control is performed is stabilized. Thus, a time is required until a synchronous establishment after an input of an input data. Also, it is difficult to estimate which number of bit the synchronization is surely established at.
Also, another clock signal producing circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei, 8-154053). As shown in
FIG. 2
, the known clock signal reproduction circuit includes an equalizer (ECL)
111
, an automatic gain controller (AGC)
112
, a low pass filter
113
, an analog-digital converter (ADC)
114
, a digital phase difference detector
115
, a VCO control voltage generator
116
and an analog VCO
117
.
An analog RF signal SIN is sampled by the ADC
114
. The digital phase difference detector
115
detects a difference between a phase of the analog RF signal and that of a clock signal CLK produced by the analog VCO
117
. The VCO control voltage generator
116
generates a control voltage based on the difference. The analog VCO
117
generates the above-mentioned clock signal CLK, which is synchronized with the analog RF signal SIN, in accordance with the control voltage. The clock signal CLK is used as a sampling signal of the ADC
114
. The clock signal CLK has a frequency satisfying the Sampling Theorem with respect to sampling the analog RF signal RIN. The ADC
114
, the digital phase difference detector
115
, the VCO control voltage generator
116
and the analog VCO
117
constitute a hybrid PLL
120
.
In the other clock signal reproducing circuit, the feedback control is performed on the analog VCO
117
, similarly to the above-mentioned clock signal producing circuit. Similarly, a certain time is required until clock signal CLK is stabilized.
Still another data identification apparatus is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei, 8-321827). As shown in
FIG. 3
, the known data identification apparatus includes a first identifying circuit
121
, a delay
16
, circuit
122
, a second identifying circuit
123
and a selector
124
.
An input signal S
in
. is inputted to the first identifying circuit
121
. The first identifying circuit
121
identifies data of the input signal S
in
, and further judges a phase relation between the input signal S
in
and a clock signal CLK.
The input signal S
in
is further inputted to the delay circuit
122
. The input signal S
in
is delayed by a certain time. The delayed input signal S
in
is inputted to the second identifying circuit
123
. The second identifying circuit
123
identifies data of the delayed input signal S
in
, and further judges a phase relation between the delayed input signal S
in
and the clock. The selector
124
, in accordance with any of the judged result of the first identifying circuit
121
and that of the second identifying circuit
123
, selects and outputs any of the identified data from the first identifying circuit
121
and that from the second identifying circuit
123
.
It is desirable that the clock signal producing circuit establishes the synchronization with an input signal in a short time after the input signal is inputted. Also, it is desirable that the synchronization is surely established before an input of a certain number of data bits in the input signal is completed.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a clock signal producing circuit producing a clock signal synchronized with an input signal, which can establish the synchronization in a short time after an input of an input signal.
Another object of the present invention is to provide a clock signal producing circuit producing a clock signal synchronized with an input signal, which surely establishes the synchronization within a predetermined number of leading bits included in the input signal after an input of an input signal.
Still another object of the present invention is to provide a clock signal producing circuit producing a clock signal synchronized with an input signal without being influenced by jitters and noises in an input signal.
Still another object of the present invention is to provide a clock signal producing circuit producing a clock signal suitable for sampling an input signal.
Still another object of the present invention is to provide a signal reproducing circuit reproducing an input signal without using a clock signal having a high frequency.
In order to achieve an aspect of the present invention, a clock signal producing apparatus is composed of a detecting circuit and a clock signal outputting circuit. The detecting circuit detects edge timings of an input signal at which the input signal is inverted. The edge timings are quantized to a predetermined number of states. The clock signal outputting circuit outputs an outputted clock signal. A phase of the outputted clock signal is adjusted based on the edge timings.
In this case, the clock signal outputting circuit may select the outputted clock signal based on the edge timings from among a plurality of clock signals whose phases are different from each other.
The clock signal producing apparatus may be further composed of a memorizing circuit. In this case, the edge timings include a present edge timing which is the latest of the edge timings, and a past edge timing which is detected before the present edge timing is detected. The memorizing circuit memorizes the past edge timing. The phase of the outputted clock signal is adjusted based on the present edge timing and the past edge timing.
In this case, the phase is desirably adjusted based on the present edge timing during a first period, and the phase is desirably adjusted based on the present edge timing and the past edge timing during a second period following the first period.
Also, the clock signal outputting circuit is desired to select the outputted clock signal based on the present edge timing and the past edge timing from among a plurality of clock signals whose phases are different from each other.
Also, the edge timings desirably includes a rising edge timing at which the input signal rises from a low level to a high level, and a falling edge timing at which an the input signal falls from the high level to the low level. In this case, the phase of the outputted clock signal is desirably adjusted bas

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