Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
1999-09-07
2001-07-24
Nu Ton, My-Trang (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S161000
Reexamination Certificate
active
06265918
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a semiconductor device for inputting and outputting a signal in synchronism with a high-speed clock signal, and more particularly, to a clock signal processing circuit and method and a semiconductor device wherein a clock signal is processed in an improved method, which are effectively used in a synchronous DRAM (Dynamic Random Access Memory).
With an increase in the operational speed of a MPU (Micro Processing Unit), an increase in the operational speed of a semiconductor memory is being required. In the case of the synchronous DRAM operable in synchronism with a clock signal, for example, data transfer at a high speed cycle of 100-200 MHz is needed.
Further, with an increase in memory capacity from 64 M-bits to 256 M-bits, the memory chip size is increased. Accordingly, when an external clock signal is taken and used as an internal clock signal, the internal clock signal may be delayed, depending upon which portion of the memory chip receives the signal.
BRIEF SUMMARY OF THE INVENTION
It is an object of the invention to provide a highly-reliable semiconductor device of a large size operable at high speed, which employs a clock signal free from a delay irrespective of a portion of a memory chip or a circuit position to which the distributed signal is applied.
To attain this object, there is provided a clock synchronizing circuit comprising: variable delay means for delaying a generated clock signal to create an internal clock signal; a detecting section for detecting a time difference between a predetermined phase of the internal clock signal and a predetermined phase of a reference clock signal; and delay amount control means for controlling a delay amount of the variable delay means to substantially eliminate the time difference, thereby substantially synchronizing the predetermined phase of the internal clock signal with the predetermined phase of the reference clock signal.
By virtue of the above structure, the phase of the internal clock signal is accurately synchronized with the phase of the reference clock signal. Further, the generated clock, which differs from the reference clock signal to be referred to for synchronization, is used to generate the internal clock signal to be synchronized with the reference clock signal. As a result, various types of signals can be used as the generated clock signal, which enables an accurately synchronized internal clock signal to be obtained using a simple structure.
REFERENCES:
patent: 4795985 (1989-01-01), Gailbreath
patent: 4847870 (1989-07-01), Butcher
patent: 5036297 (1991-07-01), Nakamura
patent: 5079519 (1992-01-01), Ashby
patent: 5101117 (1992-03-01), Johnson
patent: 5811998 (1998-09-01), Lundberg et al.
patent: 5949260 (1999-09-01), Toda
patent: 8-180678 (1996-07-01), None
patent: 8-180678A (1996-07-01), None
Banner & Witcoff , Ltd.
Kabushiki Kaisha Toshiba
Nu Ton My-Trang
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