Clock signal multiplier

Pulse or digital communications – Spread spectrum – Direct sequence

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Details

328 381, H04L 700

Patent

active

052088383

ABSTRACT:
A clock multiplier is selectable to provide either an unmultiplied input clock to the internal clock line or a multiplied clock signal, depending upon the state of a test mode input signal. By providing the circuitry on a integrated circuit chip, the chip can be driven at its normal operating frequency using lower-frequency test equipment. One multiplier device includes a plurality of series-connected one-shots.

REFERENCES:
patent: 3743946 (1973-07-01), Gass et al.
patent: 3835396 (1974-09-01), Demos et al.
patent: 3865305 (1975-02-01), Sampey
patent: 4011516 (1977-03-01), Heimbigner et al.
patent: 4353030 (1982-10-01), Nakamura et al.
patent: 4876702 (1989-10-01), Lesko

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