Clock signal multiplex circuit

Details Clock signal multiplex circuit Clock signal multiplex circuit

1993-05-03

1994-06-14

Chin, Stephen

Pulse or digital communications

Spread spectrum

Direct sequence

375110, 370108, 307480, H04J 322, H04Q 1104

Patent

active

053217284

ABSTRACT:
A multiplexer circuit for multiplexing several clock signals is controlled by at least one selection signal, and includes for each clock signal a respective delay module producing a delayed clock signal taking the value of the clock signal in response to the appearance of a predetermined switching level of the clock signal while the selection signal is in a first state and no busy signal is then present, and interrupting the delayed clock signal in response to the appearance of the switching level if the selection signal is then in a second state. The busy signal is produced whenever any of the delay module is producing a delayed clock signal, and an output signal is derived from the delayed clock signal.

REFERENCES:
patent: 4692932 (1987-09-01), Denhez et al.
patent: 4839907 (1989-06-01), Saneski

Affiliated with

Also associated with

Rating

Clock signal multiplex circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Clock signal multiplex circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock signal multiplex circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1255060