Clock signal modeling circuit with negative delay

Details Clock signal modeling circuit with negative delay Clock signal modeling circuit with negative delay

1997-06-12

1999-08-31

Ton, My-Trang Nu

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

327152, H03K 514

Patent

active

059458615

ABSTRACT:
The circuit of the present invention prevents a multi-locking phenomenon, reduces power consumption and provides an accurately locked internal clock signal. A delay unit sequentially delays an external clock signal through a plurality of unit delay terminals. A sampling and computation unit maintains the levels of signals from the unit delay terminals connected after a predetermined unit delay terminal, in which a locking phenomenon occurs, to a predetermined level when a delay clock signal among a plurality of delay clock signals from the unit delay terminals is locked. An output unit outputs a delay clock signal locked to an external clock signal in accordance with an output from the sampling and computation unit.

REFERENCES:
patent: 3248657 (1966-04-01), Turecki
patent: 3588707 (1971-06-01), Manship
patent: 3619669 (1971-11-01), Wheeler
patent: 4443766 (1984-04-01), Belton, Jr.
patent: 4618787 (1986-10-01), Jacksier et al.
patent: 4675612 (1987-06-01), Adams et al.
patent: 4677499 (1987-06-01), Shirota et al.
patent: 4713621 (1987-12-01), Nakamura et al.
patent: 5313501 (1994-05-01), Thacker
patent: 5451894 (1995-09-01), Guo
patent: 5465076 (1995-11-01), Yamauchi et al.
patent: 5467041 (1995-11-01), Baba et al.
patent: 5537069 (1996-07-01), Volk
patent: 5589788 (1996-12-01), Goto

Affiliated with

Also associated with

Rating

Clock signal modeling circuit with negative delay does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Clock signal modeling circuit with negative delay, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock signal modeling circuit with negative delay will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2427326