Clock signal generators having programmable full-period...

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Clock or pulse waveform generating

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C327S237000

Reexamination Certificate

active

06977539

ABSTRACT:
Clock signal generators include an integrated circuit chip having a PLL-based or DLL-based clock driver therein. The clock driver is configured to support generation of a plurality of clock signals having different frequencies in a range between 1 and 1/N times a frequency of an internal clock signal and full-period programmable skew characteristic, where N is a positive integer greater than one. The clock driver also includes a divide-by-N clock generator that is configured to generate N divide-by-N clock signals that have the same frequency but are phase shifted relative to each other. This clock generator operates in response to a first skew signal having a frequency equal to the frequency of the internal clock signal. A one-of-N select circuit is provided. This select circuit is configured to select one of the N divide-by-N clock signals in response to a time unit position signal. A synchronization unit is electrically coupled to an output of the divide-by-N clock generator circuit and is synchronized to the first skew signal. The synchronization unit is also coupled to an output buffer that is configured to drive an off-chip load with the selected divide-by-N clock signal having the desired skew characteristic.

REFERENCES:
patent: 5485490 (1996-01-01), Leung et al.
patent: 5614855 (1997-03-01), Lee et al.
patent: 6111445 (2000-08-01), Zerbe et al.
patent: 6125157 (2000-09-01), Donnelly et al.
patent: 6271702 (2001-08-01), Stansell
patent: 6329859 (2001-12-01), Wu
patent: 6359486 (2002-03-01), Chen
patent: 6384653 (2002-05-01), Broome
patent: 6388478 (2002-05-01), Mann
patent: 6392462 (2002-05-01), Ebuchi et al.
patent: 6433645 (2002-08-01), Mann et al.
patent: 6466098 (2002-10-01), Pickering
patent: 6509773 (2003-01-01), Buchwald et al.
patent: 6525584 (2003-02-01), Seo et al.
patent: 6539072 (2003-03-01), Donnelly et al.
patent: 6597212 (2003-07-01), Wang et al.
patent: 6608530 (2003-08-01), Green et al.
patent: 6753712 (2004-06-01), Saeki
patent: 6759886 (2004-07-01), Nakanishi
patent: 6794912 (2004-09-01), Hirata et al.
Lee et al., “A 2.5 V CMOS Delay-Locked Loop for an 18 Mbit, 500 Megabyte/s DRAM,” IEEE Journal of Solid-State Circuits, vol. 29, No. 12, Dec. 1994, pp. 1491-1496.
IDT Clock Management Products Family, Aug. 2002, Admitted Prior Art, 4 pages.
“High-Speed Multi-Phase PLL Clock Buffer,” Cypress Semiconductor Corporation, Revised Jul. 25, 2003, 14 pages.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Clock signal generators having programmable full-period... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Clock signal generators having programmable full-period..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock signal generators having programmable full-period... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3472052

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.