Clock signal generator for video signal capable of generating a

Facsimile and static presentation processing – Facsimile – Specific signal processing circuitry

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358335, 380 5, H04N 506, H04N 576

Patent

active

051212064

ABSTRACT:
A clock signal generator circuit includes a synchronous signal separation circuit for separating a synchronous signal from an input video signal; a phase-locked loop (PLL) circuit for generating a clock signal in synchronism with the synchronous signal of the video signal supplied from the separation circuit; a switch provided between the separation circuit and PLL circuit for intercepting a supply of the synchronous signal of the video signal from the separation circuit to the PLL circuit during a predetermined period; and a control circuit for further separating a vertical synchronous signal from the synchronous signal separated by the separation circuit and controlling, in accordance with the vertical synchronous signal, the switch so as to intercept a supply of the synchronous signal from the separation circuit to the PLL circuit during the predetermined period, the predetermined period being a pulse generation period during which there are present at least an equalizing pulse and dubbing preventing signal in the video signal.

REFERENCES:
patent: 4475129 (1984-10-01), Kagota
patent: 4937679 (1990-06-01), Ryan

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