Clock signal generator for a logic analyzer controlled to lock b

Details Clock signal generator for a logic analyzer controlled to lock b Clock signal generator for a logic analyzer controlled to lock b

1997-12-09

1999-08-24

Wells, Kenneth B.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327155, 327 74, 327161, 327163, H03K 5153

Patent

active

059429275

ABSTRACT:
A first comparison circuit compares an internally generated clock signal with a reference signal and produces a first error signal in response to timing differences between rising edges of the clock signal and the reference signal. A second comparison circuit compares the internally generated clock signal with the reference signal and produces a second error signal in response to timing differences between falling edges of the clock signal and the reference signal. The first and second error signals are applied to control inputs of a phase shifter chain to control delay in each stage to reduce the timing error with respect to each edge.

REFERENCES:
patent: 4922141 (1990-05-01), Lofgren
patent: 4984255 (1991-01-01), Davis
patent: 5432827 (1995-07-01), Mader
patent: 5576757 (1996-11-01), Frisch
patent: 5734301 (1998-03-01), Lee

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