Clock-signal generator for a data-processing system

Details Clock-signal generator for a data-processing system Clock-signal generator for a data-processing system

1978-01-31

1980-09-16

Shaw, Gareth D.

Boots, shoes, and leggings

328 63, 307269, G06M 302, H03K 300, G06F 104

Patent

active

042233925

ABSTRACT:
A plurality of sub-clock signals are derived from a main clock signal sou by advancing a shift register and a counter with pulses from the main clock source. The shift register is selectively loaded with a desired combination of sub-clock bits in response to a predetermined number of main clock pulses being supplied to the counter. The sub-clock signals are derived from output terminals at different stages of the shift register. The state of the sub-clock signals can be selectively frozen by decoupling pulses from the main clock source to inputs of the counter and shift register.

REFERENCES:
patent: 3418637 (1968-12-01), Humphrey
patent: 3421147 (1969-01-01), Burton et al.
patent: 3497613 (1970-02-01), Botjer et al.
patent: 3566090 (1971-02-01), Johnson
patent: 3691531 (1972-09-01), Saltini et al.
patent: 3949199 (1976-04-01), Odour
patent: 3971920 (1976-07-01), Johnson

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