Clock signal generator employing a DDS circuit

Details Clock signal generator employing a DDS circuit Clock signal generator employing a DDS circuit

2002-01-22

2003-11-04

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synthesizer

C327S150000, C327S292000, C708S271000

Reexamination Certificate

active

06642754

ABSTRACT:

BACKGROUND OF THE INVENTION
DDS (Direct Digital Synthesizer) circuits are used as modulators and synthesizers for the purpose of signal synthesis. In principle, a DDS circuit represents a clock divider with a variable divider factor; i.e., the DDS circuit divides a clock frequency supplied to it down to an arbitrarily adjustable signal frequency. For this purpose, the DDS circuit includes an accumulator which adds up or increments a frequency word applied to it, which has a certain value, and when a certain limit value is reached, i.e. in the case of an overflow, it starts from the beginning again with a corresponding residual value and outputs a clock pulse edge or a clock pulse. This clock pulse edge is used for further signal processing in the so-called pulse output DDS circuits. Pulse output DDS circuits represent a particularly simple type of DDS circuit since the clock pulse edge described above is generated directly via the carry bit or the MSB (Most Significant Bit) of the accumulator and, thus, requires neither a ROM sinewave memory nor an analog/digital converter.
However, each overflow produces an error which depends on the temporal resolution; i.e., on the clock frequency used in each case. The error caused by the limited temporal resolution of the clock signal is transferred to the carry bit or the MSB of the accumulator of the DDS circuit. This error or, respectively, the resultant jitter in the output pulse can be reduced if the clock is increased, with the output frequency remaining the same, and, accordingly, a smaller frequency word is used since the overflow limit value can be reached more accurately with a smaller frequency word which is added up more frequently. For this reason, the clock frequency of a DDS circuit should be as high as possible. However, the clock frequency is limited by the current technological possibilities. At the moment, the maximum clock frequency of a CMOS DDS circuit is about 300 MHz, the current consumption rising distinctly from only about 100 MHz. For mobile telephones, therefore, only CMOS DDS chips for clock frequencies of<100 MHz are currently on offer which, as a result, have low current consumption but, on the other hand, have a relatively strong jitter in the output pulse for the abovementioned reasons. In addition, these chips, in most cases with integrated sinewave ROM and analog/digital converter, are only provided for special applications.
As an alternative, the jitter contained in the MSB of the DDS circuit and corresponding to the clock frequency used in each case, can be suppressed or eliminated by additional signal processing measures. This, however, is extremely complex and results in a correspondingly large increase in the cost.
The present invention is, therefore, directed toward developing a clock signal generator constructed in accordance with the DDS technology described above, in such a manner that the jitter contained in the output pulse output by the clock signal generator can be effectively suppressed or at least reduced.
SUMMARY OF THE INVENTION
According to the present invention, a “fast” and a “slow” DDS circuit section are used for generating the output clock pulse or output clock pulse edge, respectively. The “slow” DDS circuit section operates with a relatively low clock frequency as usual whereas the “fast” DDS circuit section operates with a clock frequency which is higher than that of the “slow” DDS circuit section. As usual, the “slow” DDS circuit section is used for incrementing a certain frequency word and generating an output pulse when an overflow occurs. To reduce the jitter contained in the output pulse thus generated, the ideal overflow time of the “slow” DDS circuit section; i.e., the time at which no jitter would occur if the output pulse were to be generated at this time, is first determined and, depending on this, an output pulse with the higher second frequency is output at the ideal overflow time.
The jitter is reduced by using the higher clock frequency but, on the other hand, the current consumption rises only slightly since the DDS circuit section operated at the higher clock frequency operates only during the MSB overflow of the “slow” DDS circuit section; i.e., for only a short time.
The frequencies used by the two DDS circuit sections must be phase-locked to one another so that the higher frequency corresponds to an integral multiple of the lower frequency.
The “fast” DDS circuit section can be formed, for example, by an accumulator followed by a comparator so that, with the aid of the “fast DDS circuit section”, a second frequency word which is smaller than the frequency word of the “slow” DDS circuit section adds up until a count corresponding to the ideal overflow time of the “slow” DDS circuit section is reached and then outputs an output pulse, the pulse edge (MSB) of which is distinctly more accurate in time than the pulse edge generated by the “slow” DDS circuit section.
Furthermore, the “fast” DDS circuit section operated at the higher frequency can also be implemented in the form of a sigma-delta converter.
The present invention is particularly suitable, for example, for signal synthesis in mobile telephones since a low current consumption for the longest possible operating time is of particular significance in this case.


REFERENCES:
patent: 4951237 (1990-08-01), Essenwanger
patent: 5424664 (1995-06-01), Phillips
patent: 5563535 (1996-10-01), Corry et al.
patent: 5898325 (1999-04-01), Crook et al.
patent: 5963607 (1999-10-01), Romano et al.
patent: WO 96/17287 (1996-06-01), None
patent: WO 97/39529 (1997-10-01), None
patent: WO 00/07301 (2000-02-01), None

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