Clock signal generator/converter device

Details Clock signal generator/converter device Clock signal generator/converter device

2000-12-11

2003-01-21

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S147000

Reexamination Certificate

active

06509769

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a clock signal generator/converter device with the aid of which a first data signal is converted into a second data signal having a different data rate.
For data transmission protected by error correction, the data rate can be increased. At the receiving end, the original data signal can be recovered from the transmitted signal.
Thus, for example for the transmission of SDH signals (synchronous digital hierarchy) via submarine cables according to ITU-G. 975, it has recommended to introduce an error correction, for which purpose the transmission rate is increased to 15/14 of the original data rate. The use of the corresponding devices will be explained with reference to FIG.
1
. From a subscriber, a first data signal is transmitted in a first access network AN
1
. As early as here it may be necessary to use a first regenerator R
1
. The latter forwards a regenerated data signal which is transmitted in an optical network ON in a manner protected with the aid of correction bits. In the converter terminal TT, firstly an assigned clock signal is obtained from the data signal DS and the clock signal is converted into a clock signal having a higher data rate, which corresponds to the transmission rate of a second data signal DS
2
having correction bits. A further regenerator R
2
may be necessary for amplitude, pulse-shape and clock regeneration in the optical network. In the reconverter terminal TR, firstly an assigned second clock signal is obtained from the data signal DS
2
and converted into a first clock signal TS
1
, which is again assigned to the recovered first data signal DS
1
.
SUMMARY OF THE INVENTION
The object of the invention is to provide a suitable clock signal generator/converter device, in particular for the transmission terminal and the reception terminal, which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this general kind. The device is also intended to be useable in the regenerators.
With the above and other objects in view there is provided, in accordance with the invention, a clock signal generator/converter device, comprising:
a first phase-locked loop for obtaining a first clock signal from a respective one of a plurality of data signals having mutually different data rates, the first phase-locked loop receiving a respective data signal as a reference signal;
the first phase-locked loop having a feedback path with a first adjustable frequency divider for coarse matching to the different data rates;
a frequency divider connected to receive the first clock signal;
a second phase-locked loop connected to receive the first clock signal as a second reference signal via the frequency divider, the second phase-locked loop converting the first clock signal into an assigned second clock signal having a different clock frequency;
the second phase-locked loop having a feedback path with a second adjustable frequency divider for coarse matching to the different data rates of the data signals and with a third frequency divider for generating the second clock signal having the different clock frequency.
The possibility of changeover means that the novel device can be used universally. This is the essential advantage of the device. Additional advantages and features are found in the following summary.
In accordance with an added feature of the invention, a third frequency divider is connected in the feedback path of the second phase-locked loop, and the third frequency divider and the frequency divider connected between the first and second phase-locked loops are adjustable to selectively set an increase and a reduction in the clock rate of the second clock signal relative to a clock rate of the first clock signal.
In accordance with an additional feature of the invention, a further frequency divider having a fractional rational division ratio is connected in the feedback path of the second phase-locked loop.
In accordance with another feature of the invention, the division ratio of the further frequency divider is adjustable for selectively setting an increase and a reduction in the clock frequency of the second clock signal relative to a clock frequency of the first clock signal.
In accordance with a further feature of the invention, the further frequency divider is a fifth frequency divider, and a sixth frequency divider is connected downstream of the fifth frequency divider in a signal flow direction.
In accordance with again an added feature of the invention, the frequency divider in the feedback path of the second phase-locked loop is additionally adjustable to set the clock frequency of the first clock signal identical to the clock frequency of the second clock signal.
In accordance with again an additional feature of the invention, a controller is connected to and configured to adjust the frequency dividers, the controller containing information concerning the data rate of the first data signal/the clock rate of the first clock signal and the data rate of the second data signal/the clock rate of the second clock signal.
In accordance with again another feature of the invention, the data rate of the first data signal is determined by a frequency discriminator of the first phase-locked loop and a controller, and the first frequency divider of the first phase-locked loop is adjusted accordingly, and wherein the second phase-locked loop is adjusted on a basis of additional information, which may be stored or transmitted.
In accordance with a concomitant feature of the invention, there are provided identical controllable oscillators in the first and second phase-locked loops.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a clock signal generator/converter device, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.


REFERENCES:
patent: 4348769 (1982-09-01), Kittel
patent: 4608699 (1986-08-01), Batlivala et al.
patent: 4651102 (1987-03-01), Inbar
patent: 5790601 (1998-08-01), Corrigan et al.
patent: 6218876 (2001-04-01), Sung et al.
patent: 6275990 (2001-08-01), Dapper et al.
patent: 2 300 704 (1974-07-01), None
patent: 39 41 642 (1990-06-01), None
patent: 39 26 072 (1991-02-01), None
patent: 0 367 065 (1990-05-01), None
International Patent Application No. 94/18441 (Bestenreiner), dated Aug. 18, 1994.
“Forward error correction for submarine systems”, ITU-G.975, Nov. 1996, pp. 1-5.

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