Clock signal generator circuit and semiconductor integrated...

Details Clock signal generator circuit and semiconductor integrated... Clock signal generator circuit and semiconductor integrated...

2000-02-23

2003-08-19

Ton, My-Trang Nu (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S165000, C327S166000

Reexamination Certificate

active

06608514

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 11-044836, filed Feb. 23, 1999; and No. 11-044837, filed Feb. 23, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
This invention relates to a clock signal generator circuit for generating an internal clock signal synchronizing with a clock signal inputted from the outside of a chip and a semiconductor integrated circuit with the clock signal generator circuit, and more particularly to a semiconductor integrated circuit that has an off-chip driver which outputs the chip internal data outside the chip and whose operation is controlled on the basis of the clock signal generated at the clock signal generator circuit.
In the I/O section of semiconductor integrated circuits, including a semiconductor memory, such as a DRAM, the data has recently been inputted and outputted in synchronization with both of the leading edge and trailing edge of an external clock signal. Such a method is known as Double Data Rate (DDR) method. The DDR method enables data to be inputted and outputted twice as fast as a method of inputting and outputting the data in synchronization with either the leading edge or trailing edge of an external clock signal.
In a DDR type semiconductor circuit, three types of internal clock signals are generated in a chip to input and output the data in synchronization with both of the leading edge and trailing edge of an external clock signal. They are an internal clock signal Tu synchronizing with the leading edge of the external clock signal, an internal clock signal Td synchronizing with the trailing edge of the external clock signal, and an internal clock signal Tw synchronizing with both of the leading edge and trailing edge of the external clock signal.
In addition, an off-chip driver (OCD) acting as a data output circuit is provided in the I/O section of the chip. To perform output control of data, it is necessary to generate the internal clock signals, taking into account the signal delay time in the OCD, when there is a large delay time between the time a data output control internal clock signal is inputted to the OCD and the time the OCD outputs the data. Specifically, when the delay time in the OCD is so large that it cannot be ignored, it is necessary to generate an internal clock signal used to control the operation of the CD, the delay time of the OCD earlier than usual.
Various types of clock signal generator circuits for generating an internal clock signal in synchronization with an external clock signal have been considered. Of them, a Synchronous Mirror Delay (SMD) system used in “A 2.5-ns Clock Access 250-MHz 256-Mb SDRAM with a Synchronous Mirror Delay” ISSCC Digest of technical papers, pp. 374-375, February 1996 by T. Saeki, et al., and a Synchronous Adjustable Delay (SAD) system, including Synchronous Traced Backward Delay (STBD), disclosed in U.S. Pat. No. 5,867,432, issued to Haruki Toda, have been widely used because of the higher synchronous speed and less power consumption. The contents of which are incorporated herein by reference in the entirely.
The principle of a SAD clock signal generator circuit disclosed in U.S. Pat. No. 5,867,432 will be explained.
FIG. 1
is a block diagram of a SAD signal generator circuit.
The SAD signal generator circuit comprises an input buffer
11
, a delay monitor circuit
12
, a forward delay array
14
including a plurality of delay circuits
13
cascade-connected in a multistage manner, a backward delay array
16
including a plurality of delay circuits
15
cascade-connected in a multistage manner as equal the number of delay circuits
13
in the forward delay array
14
, a control circuit
17
, and an output buffer
18
to which the output of the backward delay array
16
is inputted. The control circuit
17
has as many state holding circuits (control elements) as equal the number of delay circuits in each of the forward delay array
14
and backward delay array
16
. In
FIG. 1
, the circuit composed of the forward delay array
14
, backward delay array
16
, and control circuit
17
is called a SAD circuit SAD.
FIG. 2
is a timing chart to help explain an example of the operation of the clock signal generator circuit shown in FIG.
1
. Consider a case where an external clock signal CK with a period of &tgr; is inputted to the input buffer
11
. The external clock signal CK is shaped in waveform and amplified by the input buffer
11
and the resulting signal is outputted as a pulse signal CLK. If the delay time in the input buffer
11
is D
1
, the pulse signal CLK lags behind the external clock signal CK by D
1
. The pulse signal CLK is inputted to the delay monitor circuit
12
and the control circuit
17
of the SAD circuit SAD.
The delay monitor circuit
12
has a delay time of A (=D
1
+D
2
) equal to the sum of the delay time D
1
in the input buffer
11
and the delay time D
2
in the output buffer
18
. Thus, as shown in
FIG. 2
, the pulse signal Din outputted from the delay monitor circuit
12
lags behind the pulse signal CLK outputted from the input buffer
11
by a period of A and is inputted as a signal Din to the forward delay array
14
.
The forward delay array
14
is composed of delay circuits
13
cascade-connected in a multistage manner as described earlier. During the time until the pulse signal CLK in the next cycle is inputted to the control circuit
17
, the signal Din is delayed sequentially by the multistage cascade-connected delay circuits
13
. After the pulse signal CLK in the next cycle has been inputted to the control circuit
17
, the backward delay array
16
delays the pulse signal CLK in the next cycle sequentially. On the basis of the state where the forward pulse signal propagates along the forward delay array
14
, the control circuit
17
controls the operation of the backward delay array
16
in such a manner that the propagation time of the backward pulse signal becomes equal to that of the forward pulse signal. Thus, the pulse signal CLK in the next cycle is delayed for the time (&tgr;−A) by the backward delay array
16
. The output Dout of the backward delay array
16
is delayed for the time D
2
and the resulting signal is outputted as an internal clock signal CK′.
If the delay time from when the external clock signal CK is inputted until the internal clock signal CK′ is outputted is &Dgr;
total
, then &Dgr;
total
is expressed as:
&Dgr;
total
=D
1
+A
+2(&tgr;−
A
)
+D
2
  (1)
Since D
1
+D
2
=A, &Dgr;
total
is 2&tgr; and the internal clock signal CK′ synchronize with the external clock CK, starting at the third clock in the external clock signal CK.
In the clock signal generator circuit of
FIG. 1
, when the number of delay circuits
15
in the backward delay array
16
is reduced to half the number of delay circuits
13
in the forward delay array
14
so that the delay time in the backward delay array
16
may be half the delay time in the forward delay array
14
and the delay time in the delay monitor circuit
12
is set to twice the delay time of
FIG. 1
(or to
2
A), the internal clock signal CK′ is 180° out-of-phase with the external clock signal CK.
FIG. 3
is a block diagram of a conventional SAD type clock signal generator circuit for generating an internal clock signal used to control an off-chip driver. The SAD type clock generator circuit comprises a clock control circuit
21
for generating an internal clock signal Tu synchronizing with an external clock signal CK from the external clock signal CK, a clock control circuit
22
for generating an internal clock signal Td 180° out-of-phase with the external clock signal CK, an OR circuit
23
to which the internal clock signals Tu and Td are inputted and which generates an internal clock signal Tw, and a clock control circuit
24
for generating an internal clock signal Tx of twice the frequency of the exte

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