Clock signal generator

Details Clock signal generator Clock signal generator

2001-07-03

2003-03-18

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S155000, C327S159000, C327S166000, C365S233100, C375S371000

Reexamination Certificate

active

06535044

ABSTRACT:

The invention relates to a clock signal generator for generating a clock signal with minimum phase jitter.
BACKGROUND
The generation of a clock signal by means of a DT oscillator (DTO: Discrete Timing Oscillator) is generally known.
FIG. 1
shows a DT oscillator according to the prior art, and said DT oscillator also forms part of the clock signal generator according to the invention. The DT oscillator is composed of an accumulator for adding a predefined digital incremental value which is present at a first signal input E of the accumulator to an accumulated digital value which is present at a second signal input of the accumulator and is buffered in a register of the DT oscillator. The register is connected to the output of the accumulator and is clocked with an input clock signal which has an input clock frequency f
in
. If the accumulator output value is higher than the value 2
K
−1 which can be represented on the basis of the predefined bit width K, the “overflow value” 2
K
is simply omitted.
The DTO output signal if the DT oscillator which is output at the output A is illustrated in FIG.
2
. The DT oscillator outputs a sawtooth output signal. Here, each sawtooth of the sawtooth output signal is composed of a plurality of steps with discrete amplitudes, the height of which corresponds to the incremental value applied and the width of which is determined by the clock period 1/f
in
of the applied input clock signal. When the overflow value is exceeded, the next step of the output signal A has a value which is reduced by this overflow value (modulo operation).
The sawtooth DTO output signal of the DT oscillator has a frequency f
out
in accordance with the following equation:
f
out
=f
in
*incremental/overflow value  (1)
If the frequency of the input clock signal f
in
is very high in comparison with the frequency of the output clock signal f
out
, the most significant bit MSB of the DTO output signal can be used directly as a clock output signal. The direct use of the most significant bit MSB of the DT oscillator means that this method of implementation requires very little expenditure in terms of circuitry. However, the direct use of the most significant bit MSB of the digital output signal of the DT oscillator has the disadvantage that relatively high phase jitter occurs.
FIG. 3
shows the cause of the phase jitter which occurs at the signal output A of the DT oscillator illustrated in FIG.
1
. The DTO output signal is represented by sampled values. The position of the sampling times migrates over the sawtooth output signal of the DT oscillator because the ratio of the output frequency f
out
to the clock frequency of the input signal f
in
is rational. The most significant bit MSB of the DT oscillator which is used as the output clock signal changes at a sampling time. The change in the most significant bit MSB of the DT oscillator, and thus the signal edges of the output clock signal, therefore deviate from the ideal phase relation. The ideal phase relation is given by that time at which the sawtooth output signal of the DT oscillator jumps from the overflow value to the value 0.
The case A illustrated in
FIG. 3
, with the sampled values a
1
, a
2
, constitutes one of the limiting cases, while the case B with the sampled values b
1
, b
2
shows the other limiting case.
In the limiting case shown in case A, the sampled value a
1
lies precisely at the value of the overflow value/incremental value. As a result of the incremental value being added to the sampled value a
1
, the sawtooth output signal reaches precisely the overflow value, with the result that the sawtooth output signal jumps back to the sampled value a
2
, that is to say to the digital value 0.
In the limiting case shown in case B, the sawtooth output signal has the sampled value b
1
which corresponds precisely to the overflow value −1. As a result of the incremental value being accumulated, an overflow occurs and the digital value b
2
is output at the output of the DT oscillator.
As is apparent from
FIG. 3
, the maximum phase jitter is:
Jitter
max
=1/f
in
  (2)
The higher the input clock frequency f
in
, the lower the phase displacement. However, the frequency of the input clock signal which is generated for example by a quartz oscillator and an analog pLL circuit can be increased only to a limited degree.
FIG. 4
shows an example of the phase displacements which occur with a conventional DT oscillator in which the ratio of the input frequency f
in
of the input clock signal with respect to the frequency of the output clock signal f
out
is 3.4.
FIG. 4
shows a sawtooth profile of the DTO output signal and the signal profile of the associated most significant bit MSB of the DT oscillator.
The ideal phase relation is determined by the time at which an overflow occurs in the DT oscillator and the digital output signal jumps back to the value 0. The real phase relation of the DT oscillator is determined by the time at which the most significant bit MSB of the digital output signal has a falling signal edge.
SUMMARY
The following applies to the chronological displacement between the real phase relation t
real
and the ideal phase relation t
ideal
:
&Dgr;t=t
real
−t
ideal
=T
in
*DTO
n0
/incremental value  (3)
T
in
being the clock period of the input clock signal, that is to say:
T
in
=1/f
in
  (4)
and DTO
n0
being the digital value of the DT oscillator after an overflow has occurred.
The DTO digital value after each overflow thus constitutes a measure of the time or phase displacement between the ideal signal phase of the DTO output signal and the signal phase of the most significant bit of the DTO output signal, it being possible to use the most significant bit MSB of the DTO output signal as a clock output signal.
For the chronological displacement after the DTO output value has the exceeded the value ½*overflow, the following applies:
&Dgr;t=t
real
−t
ideal
=T
in
*(DTO
nn0
−½ overflow value )/increment
The object of the present invention is therefore to provide a clock signal generator for generating a clock signal with a minimum phase jitter, in which the clock signal acquired from the most significant signal bit of a DT oscillator has a minimum phase displacement with respect to the DTO output signal.
The invention provides a clock signal generator for generating a clock signal with minimum phase jitter at a clock signal generator output, the clock signal generator having:
a DT oscillator which is clocked with an input clock signal and which generates a periodic digital DTO output signal,
a phase displacement calculation unit for calculating the phase displacement between the signal phase of the DTO output signal and the signal phase of the most significant bit of the DTO output signal, and
a phase displacement reduction unit for reducing the phase displacement between the signal phase of the DTO output signal and the signal phase of the most significant bit of the DTO output signal as a function of the calculated phase displacement, the most significant bit being output with reduced signal displacement as a clock signal at the clock signal generator output.
The DT oscillator preferably has an accumulator for adding a digital incremental value which is present at a first signal input of the accumulator to a buffered accumulated digital value which is present at a second signal input of the accumulator.
The DT oscillator preferably has a register which is connected to a signal output of the accumulator in order to buffer the accumulated digital value.
The register of the DT oscillator is preferably clocked by the input clock signal with an input clock frequency f
in
in order to generate the digital DTO output signal.
The register of the DT oscillator is preferably reset if the accumulated digital value reaches a digital overflow value.
In one preferred embodiment of the clock signal generator according to the invention, the phase displacement calculation unit

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