Clock-signal generator

Details Clock-signal generator Clock-signal generator

2011-03-08

2011-03-08

Luu, An T (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Rectangular or pulse waveform width control

C327S172000, C327S176000

Reexamination Certificate

active

07902893

ABSTRACT:
A clock-signal generating unit for generating an output clock signal with a controlled duty cycle based on an input clock signal. The clock-signal generating unit comprises one or more delay lines arranged to generate a plurality of mutually delayed output signals at different positions within the delay line based on the input clock signal. A control unit is arranged to detect a position within one of the delay lines, the output signal of which has a delay, with respect to the input clock signal, that is essentially equal to one period of the input clock signal, and generate an output signal that indicates the detected position. A selection unit is arranged to generate a delayed clock signal that has a delay, with respect to a signal associated with the input clock signal, that is essentially equal to a period of the clock signal multiplied with said duty cycle based on output signals from one of the delay lines and the output signal of the control unit. The clock-signal generating unit comprises circuitry for generating the output clock signal based on the signal associated with the input clock signal and the delayed clock signal. A corresponding method of generating an output clock signal with a controlled duty cycle based on an input clock signal is also disclosed.

REFERENCES:
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patent: 2004/0085111 (2004-05-01), Yi
patent: 2006/0044037 (2006-03-01), Gomm et al.
patent: 2006/0227861 (2006-10-01), Maksimovic
patent: 0 522 274 (1993-01-01), None
European Search Report, corresponding to EP 08 15 6869, date of completion of the search Aug. 14, 2008.

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