Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2006-02-28
2010-02-02
Le, Thong Q (Department: 2827)
Static information storage and retrieval
Addressing
Sync/clocking
C365S233110, C365S233120, C365S233170
Reexamination Certificate
active
07656743
ABSTRACT:
This disclosure describes a clock circuit for a memory controller. The described circuit uses a processor clock signal to generate an input clock signal for use during write operations to the memory, or to generate a feedback clock signal for use during read operations from the memory. The circuit is particularly applicable to mobile wireless devices that include memories that do not generate a strobe. The clock circuit may comprise a driver in series with a resistor element that generates an input clock signal for input to a memory, and a resistor-capacitor (RC) filter in series with a receiver that generates a feedback clock signal for output from the memory, wherein an input to the RC filter is tapped between the driver and the resistor element.
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International Search Report, PCT/US2006/060797 - International Search Authority - European Patent Office, May 3, 2007.
Written Opinion, PCT/US2006/060797 - International Search Authority - European Patent Office, May 3, 2007.
Kapoor Sanat
Maddali Srinivas
Mohan Vivek
Srinivas Vaishnav
Jenckes Kenyon
Le Thong Q
Mobarhan Ramin
QUALCOMM Incorporated
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