Clock signal generation circuit used for sample hold circuit

Details Clock signal generation circuit used for sample hold circuit Clock signal generation circuit used for sample hold circuit

2005-07-19

2005-07-19

Nguyen, Minh (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S258000

Reexamination Certificate

active

06919750

ABSTRACT:
A master DLL circuit (3) generates a first delay signal (CKD) by delaying the master clock signal by a first delay time (T0) and generates a first pulse signal (Smp) having a pulse width (T0) of the first delay time, and generates a first control signal (Scp) which is changed in accordance with the first pulse signal (Smp), and adjusts the first delay time (T0) in accordance with the first control signal (Scp). Each slave DLL circuit (D1to Dm) delays, by a second delay time (td), a delay internal clock signal, and outputs the delayed delay internal clock signals (CK1to CKm) which form the multiphase clock signals. Each slave DLL circuit generates a second pulse signal (Ssp) having a pulse width (td) of the second delay time, and generates a second control signal (Scp1) which is changed in accordance with the first and second pulse signals (Smp, Ssp), and adjusts the second delay time (td) in accordance with the second control signal (Scp1), thus reducing a skew value of the multiphase clock signal.

REFERENCES:
patent: 3596188 (1971-07-01), Hasse
patent: 3735277 (1973-05-01), Wanlass
patent: 5087829 (1992-02-01), Ishibashi et al.
patent: 5532633 (1996-07-01), Kawai
patent: 6137336 (2000-10-01), Baba et al.
Technical Digest p. 396, p. 397 and p. 470 of International Solid-State Circuit Conference of US Institute of Electrical and Electronics Engineers. Lin Wu et al (Feb., 2001).

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